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-rw-r--r--src/core/arm/interpreter/armcopro.cpp142
-rw-r--r--src/core/arm/interpreter/arminit.cpp97
-rw-r--r--src/core/arm/interpreter/armsupp.cpp428
3 files changed, 494 insertions, 173 deletions
diff --git a/src/core/arm/interpreter/armcopro.cpp b/src/core/arm/interpreter/armcopro.cpp
deleted file mode 100644
index 4ae0c52e4..000000000
--- a/src/core/arm/interpreter/armcopro.cpp
+++ /dev/null
@@ -1,142 +0,0 @@
-/* armcopro.c -- co-processor interface: ARM6 Instruction Emulator.
- Copyright (C) 1994, 2000 Advanced RISC Machines Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-
-#include "core/arm/skyeye_common/armdefs.h"
-#include "core/arm/skyeye_common/armemu.h"
-#include "core/arm/skyeye_common/vfp/vfp.h"
-
-// Dummy Co-processors.
-
-static unsigned int NoCoPro3R(ARMul_State* state, unsigned int a, ARMword b)
-{
- return ARMul_CANT;
-}
-
-static unsigned int NoCoPro4R(ARMul_State* state, unsigned int a, ARMword b, ARMword c)
-{
- return ARMul_CANT;
-}
-
-static unsigned int NoCoPro4W(ARMul_State* state, unsigned int a, ARMword b, ARMword* c)
-{
- return ARMul_CANT;
-}
-
-static unsigned int NoCoPro5R(ARMul_State* state, unsigned int a, ARMword b, ARMword c, ARMword d)
-{
- return ARMul_CANT;
-}
-
-static unsigned int NoCoPro5W(ARMul_State* state, unsigned int a, ARMword b, ARMword* c, ARMword* d)
-{
- return ARMul_CANT;
-}
-
-// Install co-processor instruction handlers in this routine.
-void ARMul_CoProInit(ARMul_State* state)
-{
- // Initialise tham all first.
- for (unsigned int i = 0; i < 16; i++)
- ARMul_CoProDetach(state, i);
-
- // Install CoPro Instruction handlers here.
- // The format is:
- // ARMul_CoProAttach (state, CP Number, Init routine, Exit routine
- // LDC routine, STC routine, MRC routine, MCR routine,
- // CDP routine, Read Reg routine, Write Reg routine).
- if (state->is_v6) {
- ARMul_CoProAttach(state, 10, VFPInit, NULL, VFPLDC, VFPSTC,
- VFPMRC, VFPMCR, VFPMRRC, VFPMCRR, VFPCDP, NULL, NULL);
- ARMul_CoProAttach(state, 11, VFPInit, NULL, VFPLDC, VFPSTC,
- VFPMRC, VFPMCR, VFPMRRC, VFPMCRR, VFPCDP, NULL, NULL);
-
- /*ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL,
- MMUMRC, MMUMCR, NULL, NULL, NULL, NULL, NULL);*/
- }
-
- // No handlers below here.
-
- // Call all the initialisation routines.
- for (unsigned int i = 0; i < 16; i++) {
- if (state->CPInit[i])
- (state->CPInit[i]) (state);
- }
-}
-
-// Install co-processor finalisation routines in this routine.
-void ARMul_CoProExit(ARMul_State * state)
-{
- for (unsigned int i = 0; i < 16; i++)
- if (state->CPExit[i])
- (state->CPExit[i]) (state);
-
- // Detach all handlers.
- for (unsigned int i = 0; i < 16; i++)
- ARMul_CoProDetach(state, i);
-}
-
-// Routines to hook Co-processors into ARMulator.
-
-void
-ARMul_CoProAttach(ARMul_State* state,
-unsigned number,
-ARMul_CPInits* init,
-ARMul_CPExits* exit,
-ARMul_LDCs* ldc,
-ARMul_STCs* stc,
-ARMul_MRCs* mrc,
-ARMul_MCRs* mcr,
-ARMul_MRRCs* mrrc,
-ARMul_MCRRs* mcrr,
-ARMul_CDPs* cdp,
-ARMul_CPReads* read, ARMul_CPWrites* write)
-{
- if (init != NULL)
- state->CPInit[number] = init;
- if (exit != NULL)
- state->CPExit[number] = exit;
- if (ldc != NULL)
- state->LDC[number] = ldc;
- if (stc != NULL)
- state->STC[number] = stc;
- if (mrc != NULL)
- state->MRC[number] = mrc;
- if (mcr != NULL)
- state->MCR[number] = mcr;
- if (mrrc != NULL)
- state->MRRC[number] = mrrc;
- if (mcrr != NULL)
- state->MCRR[number] = mcrr;
- if (cdp != NULL)
- state->CDP[number] = cdp;
- if (read != NULL)
- state->CPRead[number] = read;
- if (write != NULL)
- state->CPWrite[number] = write;
-}
-
-void ARMul_CoProDetach(ARMul_State* state, unsigned number)
-{
- ARMul_CoProAttach(state, number, NULL, NULL,
- NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
- NoCoPro5W, NoCoPro5R, NoCoPro3R, NULL, NULL);
-
- state->CPInit[number] = NULL;
- state->CPExit[number] = NULL;
- state->CPRead[number] = NULL;
- state->CPWrite[number] = NULL;
-}
diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp
index 4ac827e0a..680a94a39 100644
--- a/src/core/arm/interpreter/arminit.cpp
+++ b/src/core/arm/interpreter/arminit.cpp
@@ -18,31 +18,16 @@
#include <cstring>
#include "core/arm/skyeye_common/armdefs.h"
#include "core/arm/skyeye_common/armemu.h"
+#include "core/arm/skyeye_common/vfp/vfp.h"
/***************************************************************************\
* Returns a new instantiation of the ARMulator's state *
\***************************************************************************/
ARMul_State* ARMul_NewState(ARMul_State* state)
{
- memset(state, 0, sizeof(ARMul_State));
-
state->Emulate = RUN;
- for (unsigned int i = 0; i < 16; i++) {
- state->Reg[i] = 0;
- for (unsigned int j = 0; j < 7; j++)
- state->RegBank[j][i] = 0;
- }
- for (unsigned int i = 0; i < 7; i++)
- state->Spsr[i] = 0;
-
state->Mode = USER32MODE;
- state->VectorCatch = 0;
- state->Aborted = false;
- state->Reseted = false;
- state->Inted = 3;
- state->LastInted = 3;
-
state->lateabtSig = HIGH;
state->bigendSig = LOW;
@@ -55,15 +40,69 @@ ARMul_State* ARMul_NewState(ARMul_State* state)
void ARMul_SelectProcessor(ARMul_State* state, unsigned properties)
{
- state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) != 0;
- state->is_v5 = (properties & ARM_v5_Prop) != 0;
- state->is_v5e = (properties & ARM_v5e_Prop) != 0;
- state->is_v6 = (properties & ARM_v6_Prop) != 0;
- state->is_v7 = (properties & ARM_v7_Prop) != 0;
-
- // Only initialse the coprocessor support once we
- // know what kind of chip we are dealing with.
- ARMul_CoProInit(state);
+ state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) != 0;
+ state->is_v5 = (properties & ARM_v5_Prop) != 0;
+ state->is_v5e = (properties & ARM_v5e_Prop) != 0;
+ state->is_v6 = (properties & ARM_v6_Prop) != 0;
+ state->is_v7 = (properties & ARM_v7_Prop) != 0;
+}
+
+// Resets certain MPCore CP15 values to their ARM-defined reset values.
+static void ResetMPCoreCP15Registers(ARMul_State* cpu)
+{
+ // c0
+ cpu->CP15[CP15_MAIN_ID] = 0x410FB024;
+ cpu->CP15[CP15_TLB_TYPE] = 0x00000800;
+ cpu->CP15[CP15_PROCESSOR_FEATURE_0] = 0x00000111;
+ cpu->CP15[CP15_PROCESSOR_FEATURE_1] = 0x00000001;
+ cpu->CP15[CP15_DEBUG_FEATURE_0] = 0x00000002;
+ cpu->CP15[CP15_MEMORY_MODEL_FEATURE_0] = 0x01100103;
+ cpu->CP15[CP15_MEMORY_MODEL_FEATURE_1] = 0x10020302;
+ cpu->CP15[CP15_MEMORY_MODEL_FEATURE_2] = 0x01222000;
+ cpu->CP15[CP15_MEMORY_MODEL_FEATURE_3] = 0x00000000;
+ cpu->CP15[CP15_ISA_FEATURE_0] = 0x00100011;
+ cpu->CP15[CP15_ISA_FEATURE_1] = 0x12002111;
+ cpu->CP15[CP15_ISA_FEATURE_2] = 0x11221011;
+ cpu->CP15[CP15_ISA_FEATURE_3] = 0x01102131;
+ cpu->CP15[CP15_ISA_FEATURE_4] = 0x00000141;
+
+ // c1
+ cpu->CP15[CP15_CONTROL] = 0x00054078;
+ cpu->CP15[CP15_AUXILIARY_CONTROL] = 0x0000000F;
+ cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = 0x00000000;
+
+ // c2
+ cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0] = 0x00000000;
+ cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1] = 0x00000000;
+ cpu->CP15[CP15_TRANSLATION_BASE_CONTROL] = 0x00000000;
+
+ // c3
+ cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL] = 0x00000000;
+
+ // c7
+ cpu->CP15[CP15_PHYS_ADDRESS] = 0x00000000;
+
+ // c9
+ cpu->CP15[CP15_DATA_CACHE_LOCKDOWN] = 0xFFFFFFF0;
+
+ // c10
+ cpu->CP15[CP15_TLB_LOCKDOWN] = 0x00000000;
+ cpu->CP15[CP15_PRIMARY_REGION_REMAP] = 0x00098AA4;
+ cpu->CP15[CP15_NORMAL_REGION_REMAP] = 0x44E048E0;
+
+ // c13
+ cpu->CP15[CP15_PID] = 0x00000000;
+ cpu->CP15[CP15_CONTEXT_ID] = 0x00000000;
+ cpu->CP15[CP15_THREAD_UPRW] = 0x00000000;
+ cpu->CP15[CP15_THREAD_URO] = 0x00000000;
+ cpu->CP15[CP15_THREAD_PRW] = 0x00000000;
+
+ // c15
+ cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = 0x00000000;
+ cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = 0x00000000;
+ cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = 0x00000000;
+ cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = 0x00000000;
+ cpu->CP15[CP15_TLB_DEBUG_CONTROL] = 0x00000000;
}
/***************************************************************************\
@@ -71,24 +110,20 @@ void ARMul_SelectProcessor(ARMul_State* state, unsigned properties)
\***************************************************************************/
void ARMul_Reset(ARMul_State* state)
{
- state->NextInstr = 0;
+ VFPInit(state);
state->Reg[15] = 0;
state->Cpsr = INTBITS | SVC32MODE;
state->Mode = SVC32MODE;
-
state->Bank = SVCBANK;
- FLUSHPIPE;
- state->EndCondition = 0;
- state->ErrorCode = 0;
+ ResetMPCoreCP15Registers(state);
state->NresetSig = HIGH;
state->NfiqSig = HIGH;
state->NirqSig = HIGH;
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
state->abortSig = LOW;
- state->AbortAddr = 1;
state->NumInstrs = 0;
}
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp
index aca2bfbbd..1b078dc71 100644
--- a/src/core/arm/interpreter/armsupp.cpp
+++ b/src/core/arm/interpreter/armsupp.cpp
@@ -15,7 +15,11 @@
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+#include "common/logging/log.h"
+
+#include "core/mem_map.h"
#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/arm_regformat.h"
// Unsigned sum of absolute difference
u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right)
@@ -207,3 +211,427 @@ bool InBigEndianMode(ARMul_State* cpu)
{
return (cpu->Cpsr & (1 << 9)) != 0;
}
+
+// Whether or not the given CPU is in a mode other than user mode.
+bool InAPrivilegedMode(ARMul_State* cpu)
+{
+ return (cpu->Mode != USER32MODE);
+}
+
+// Reads from the CP15 registers. Used with implementation of the MRC instruction.
+// Note that since the 3DS does not have the hypervisor extensions, these registers
+// are not implemented.
+u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2)
+{
+ // Unprivileged registers
+ if (crn == 13 && opcode_1 == 0 && crm == 0)
+ {
+ if (opcode_2 == 2)
+ return cpu->CP15[CP15_THREAD_UPRW];
+
+ if (opcode_2 == 3)
+ return cpu->CP15[CP15_THREAD_URO];
+ }
+
+ if (InAPrivilegedMode(cpu))
+ {
+ if (crn == 0 && opcode_1 == 0)
+ {
+ if (crm == 0)
+ {
+ if (opcode_2 == 0)
+ return cpu->CP15[CP15_MAIN_ID];
+
+ if (opcode_2 == 1)
+ return cpu->CP15[CP15_CACHE_TYPE];
+
+ if (opcode_2 == 3)
+ return cpu->CP15[CP15_TLB_TYPE];
+
+ if (opcode_2 == 5)
+ return cpu->CP15[CP15_CPU_ID];
+ }
+ else if (crm == 1)
+ {
+ if (opcode_2 == 0)
+ return cpu->CP15[CP15_PROCESSOR_FEATURE_0];
+
+ if (opcode_2 == 1)
+ return cpu->CP15[CP15_PROCESSOR_FEATURE_1];
+
+ if (opcode_2 == 2)
+ return cpu->CP15[CP15_DEBUG_FEATURE_0];
+
+ if (opcode_2 == 4)
+ return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_0];
+
+ if (opcode_2 == 5)
+ return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_1];
+
+ if (opcode_2 == 6)
+ return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_2];
+
+ if (opcode_2 == 7)
+ return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_3];
+ }
+ else if (crm == 2)
+ {
+ if (opcode_2 == 0)
+ return cpu->CP15[CP15_ISA_FEATURE_0];
+
+ if (opcode_2 == 1)
+ return cpu->CP15[CP15_ISA_FEATURE_1];
+
+ if (opcode_2 == 2)
+ return cpu->CP15[CP15_ISA_FEATURE_2];
+
+ if (opcode_2 == 3)
+ return cpu->CP15[CP15_ISA_FEATURE_3];
+
+ if (opcode_2 == 4)
+ return cpu->CP15[CP15_ISA_FEATURE_4];
+ }
+ }
+
+ if (crn == 1 && opcode_1 == 0 && crm == 0)
+ {
+ if (opcode_2 == 0)
+ return cpu->CP15[CP15_CONTROL];
+
+ if (opcode_2 == 1)
+ return cpu->CP15[CP15_AUXILIARY_CONTROL];
+
+ if (opcode_2 == 2)
+ return cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL];
+ }
+
+ if (crn == 2 && opcode_1 == 0 && crm == 0)
+ {
+ if (opcode_2 == 0)
+ return cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0];
+
+ if (opcode_2 == 1)
+ return cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1];
+
+ if (opcode_2 == 2)
+ return cpu->CP15[CP15_TRANSLATION_BASE_CONTROL];
+ }
+
+ if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
+ return cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL];
+
+ if (crn == 5 && opcode_1 == 0 && crm == 0)
+ {
+ if (opcode_2 == 0)
+ return cpu->CP15[CP15_FAULT_STATUS];
+
+ if (opcode_2 == 1)
+ return cpu->CP15[CP15_INSTR_FAULT_STATUS];
+ }
+
+ if (crn == 6 && opcode_1 == 0 && crm == 0)
+ {
+ if (opcode_2 == 0)
+ return cpu->CP15[CP15_FAULT_ADDRESS];
+
+ if (opcode_2 == 1)
+ return cpu->CP15[CP15_WFAR];
+ }
+
+ if (crn == 7 && opcode_1 == 0 && crm == 4 && opcode_2 == 0)
+ return cpu->CP15[CP15_PHYS_ADDRESS];
+
+ if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
+ return cpu->CP15[CP15_DATA_CACHE_LOCKDOWN];
+
+ if (crn == 10 && opcode_1 == 0)
+ {
+ if (crm == 0 && opcode_2 == 0)
+ return cpu->CP15[CP15_TLB_LOCKDOWN];
+
+ if (crm == 2)
+ {
+ if (opcode_2 == 0)
+ return cpu->CP15[CP15_PRIMARY_REGION_REMAP];
+
+ if (opcode_2 == 1)
+ return cpu->CP15[CP15_NORMAL_REGION_REMAP];
+ }
+ }
+
+ if (crn == 13 && crm == 0)
+ {
+ if (opcode_2 == 0)
+ return cpu->CP15[CP15_PID];
+
+ if (opcode_2 == 1)
+ return cpu->CP15[CP15_CONTEXT_ID];
+
+ if (opcode_2 == 4)
+ return cpu->CP15[CP15_THREAD_PRW];
+ }
+
+ if (crn == 15)
+ {
+ if (opcode_1 == 0 && crm == 12)
+ {
+ if (opcode_2 == 0)
+ return cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL];
+
+ if (opcode_2 == 1)
+ return cpu->CP15[CP15_CYCLE_COUNTER];
+
+ if (opcode_2 == 2)
+ return cpu->CP15[CP15_COUNT_0];
+
+ if (opcode_2 == 3)
+ return cpu->CP15[CP15_COUNT_1];
+ }
+
+ if (opcode_1 == 5 && opcode_2 == 2)
+ {
+ if (crm == 5)
+ return cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS];
+
+ if (crm == 6)
+ return cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS];
+
+ if (crm == 7)
+ return cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE];
+ }
+
+ if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)
+ return cpu->CP15[CP15_TLB_DEBUG_CONTROL];
+ }
+ }
+
+ LOG_ERROR(Core_ARM11, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", crn, crm, opcode_1, opcode_2);
+ return 0;
+}
+
+// Write to the CP15 registers. Used with implementation of the MCR instruction.
+// Note that since the 3DS does not have the hypervisor extensions, these registers
+// are not implemented.
+void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2)
+{
+ if (InAPrivilegedMode(cpu))
+ {
+ if (crn == 1 && opcode_1 == 0 && crm == 0)
+ {
+ if (opcode_2 == 0)
+ cpu->CP15[CP15_CONTROL] = value;
+ else if (opcode_2 == 1)
+ cpu->CP15[CP15_AUXILIARY_CONTROL] = value;
+ else if (opcode_2 == 2)
+ cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = value;
+ }
+ else if (crn == 2 && opcode_1 == 0 && crm == 0)
+ {
+ if (opcode_2 == 0)
+ cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0] = value;
+ else if (opcode_2 == 1)
+ cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1] = value;
+ else if (opcode_2 == 2)
+ cpu->CP15[CP15_TRANSLATION_BASE_CONTROL] = value;
+ }
+ else if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
+ {
+ cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL] = value;
+ }
+ else if (crn == 5 && opcode_1 == 0 && crm == 0)
+ {
+ if (opcode_2 == 0)
+ cpu->CP15[CP15_FAULT_STATUS] = value;
+ else if (opcode_2 == 1)
+ cpu->CP15[CP15_INSTR_FAULT_STATUS] = value;
+ }
+ else if (crn == 6 && opcode_1 == 0 && crm == 0)
+ {
+ if (opcode_2 == 0)
+ cpu->CP15[CP15_FAULT_ADDRESS] = value;
+ else if (opcode_2 == 1)
+ cpu->CP15[CP15_WFAR] = value;
+ }
+ else if (crn == 7 && opcode_1 == 0)
+ {
+ if (crm == 0 && opcode_2 == 4)
+ {
+ cpu->CP15[CP15_WAIT_FOR_INTERRUPT] = value;
+ }
+ else if (crm == 4 && opcode_2 == 0)
+ {
+ // NOTE: Not entirely accurate. This should do permission checks.
+ cpu->CP15[CP15_PHYS_ADDRESS] = Memory::VirtualToPhysicalAddress(value);
+ }
+ else if (crm == 5)
+ {
+ if (opcode_2 == 0)
+ cpu->CP15[CP15_INVALIDATE_INSTR_CACHE] = value;
+ else if (opcode_2 == 1)
+ cpu->CP15[CP15_INVALIDATE_INSTR_CACHE_USING_MVA] = value;
+ else if (opcode_2 == 2)
+ cpu->CP15[CP15_INVALIDATE_INSTR_CACHE_USING_INDEX] = value;
+ else if (opcode_2 == 6)
+ cpu->CP15[CP15_FLUSH_BRANCH_TARGET_CACHE] = value;
+ else if (opcode_2 == 7)
+ cpu->CP15[CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY] = value;
+ }
+ else if (crm == 6)
+ {
+ if (opcode_2 == 0)
+ cpu->CP15[CP15_INVALIDATE_DATA_CACHE] = value;
+ else if (opcode_2 == 1)
+ cpu->CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA] = value;
+ else if (opcode_2 == 2)
+ cpu->CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value;
+ }
+ else if (crm == 7 && opcode_2 == 0)
+ {
+ cpu->CP15[CP15_INVALIDATE_DATA_AND_INSTR_CACHE] = value;
+ }
+ else if (crm == 10)
+ {
+ if (opcode_2 == 0)
+ cpu->CP15[CP15_CLEAN_DATA_CACHE] = value;
+ else if (opcode_2 == 1)
+ cpu->CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_MVA] = value;
+ else if (opcode_2 == 2)
+ cpu->CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX] = value;
+ }
+ else if (crm == 14)
+ {
+ if (opcode_2 == 0)
+ cpu->CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE] = value;
+ else if (opcode_2 == 1)
+ cpu->CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA] = value;
+ else if (opcode_2 == 2)
+ cpu->CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value;
+ }
+ }
+ else if (crn == 8 && opcode_1 == 0)
+ {
+ LOG_WARNING(Core_ARM11, "TLB operations not fully implemented.");
+
+ if (crm == 5)
+ {
+ if (opcode_2 == 0)
+ cpu->CP15[CP15_INVALIDATE_ITLB] = value;
+ else if (opcode_2 == 1)
+ cpu->CP15[CP15_INVALIDATE_ITLB_SINGLE_ENTRY] = value;
+ else if (opcode_2 == 2)
+ cpu->CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH] = value;
+ else if (opcode_2 == 3)
+ cpu->CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_MVA] = value;
+ }
+ else if (crm == 6)
+ {
+ if (opcode_2 == 0)
+ cpu->CP15[CP15_INVALIDATE_DTLB] = value;
+ else if (opcode_2 == 1)
+ cpu->CP15[CP15_INVALIDATE_DTLB_SINGLE_ENTRY] = value;
+ else if (opcode_2 == 2)
+ cpu->CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH] = value;
+ else if (opcode_2 == 3)
+ cpu->CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_MVA] = value;
+ }
+ else if (crm == 7)
+ {
+ if (opcode_2 == 0)
+ cpu->CP15[CP15_INVALIDATE_UTLB] = value;
+ else if (opcode_2 == 1)
+ cpu->CP15[CP15_INVALIDATE_UTLB_SINGLE_ENTRY] = value;
+ else if (opcode_2 == 2)
+ cpu->CP15[CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH] = value;
+ else if (opcode_2 == 3)
+ cpu->CP15[CP15_INVALIDATE_UTLB_ENTRY_ON_MVA] = value;
+ }
+ }
+ else if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
+ {
+ cpu->CP15[CP15_DATA_CACHE_LOCKDOWN] = value;
+ }
+ else if (crn == 10 && opcode_1 == 0)
+ {
+ if (crm == 0 && opcode_2 == 0)
+ {
+ cpu->CP15[CP15_TLB_LOCKDOWN] = value;
+ }
+ else if (crm == 2)
+ {
+ if (opcode_2 == 0)
+ cpu->CP15[CP15_PRIMARY_REGION_REMAP] = value;
+ else if (opcode_2 == 1)
+ cpu->CP15[CP15_NORMAL_REGION_REMAP] = value;
+ }
+ }
+ else if (crn == 13 && opcode_1 == 0 && crm == 0)
+ {
+ if (opcode_2 == 0)
+ cpu->CP15[CP15_PID] = value;
+ else if (opcode_2 == 1)
+ cpu->CP15[CP15_CONTEXT_ID] = value;
+ else if (opcode_2 == 3)
+ cpu->CP15[CP15_THREAD_URO] = value;
+ else if (opcode_2 == 4)
+ cpu->CP15[CP15_THREAD_PRW] = value;
+ }
+ else if (crn == 15)
+ {
+ if (opcode_1 == 0 && crm == 12)
+ {
+ if (opcode_2 == 0)
+ cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = value;
+ else if (opcode_2 == 1)
+ cpu->CP15[CP15_CYCLE_COUNTER] = value;
+ else if (opcode_2 == 2)
+ cpu->CP15[CP15_COUNT_0] = value;
+ else if (opcode_2 == 3)
+ cpu->CP15[CP15_COUNT_1] = value;
+ }
+ else if (opcode_1 == 5)
+ {
+ if (crm == 4)
+ {
+ if (opcode_2 == 2)
+ cpu->CP15[CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY] = value;
+ else if (opcode_2 == 4)
+ cpu->CP15[CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY] = value;
+ }
+ else if (crm == 5 && opcode_2 == 2)
+ {
+ cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = value;
+ }
+ else if (crm == 6 && opcode_2 == 2)
+ {
+ cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = value;
+ }
+ else if (crm == 7 && opcode_2 == 2)
+ {
+ cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = value;
+ }
+ }
+ else if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)
+ {
+ cpu->CP15[CP15_TLB_DEBUG_CONTROL] = value;
+ }
+ }
+ }
+
+ // Unprivileged registers
+ if (crn == 7 && opcode_1 == 0 && crm == 5 && opcode_2 == 4)
+ {
+ cpu->CP15[CP15_FLUSH_PREFETCH_BUFFER] = value;
+ }
+ else if (crn == 7 && opcode_1 == 0 && crm == 10)
+ {
+ if (opcode_2 == 4)
+ cpu->CP15[CP15_DATA_SYNC_BARRIER] = value;
+ else if (opcode_2 == 5)
+ cpu->CP15[CP15_DATA_MEMORY_BARRIER] = value;
+
+ }
+ else if (crn == 13 && opcode_1 == 0 && crm == 0 && opcode_2 == 2)
+ {
+ cpu->CP15[CP15_THREAD_UPRW] = value;
+ }
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 05:12:33 +0100