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Diffstat (limited to 'src/core/arm/interpreter/armemu.cpp')
-rw-r--r--src/core/arm/interpreter/armemu.cpp139
1 files changed, 98 insertions, 41 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 610e04f10..b2f671f94 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -1670,7 +1670,7 @@ mainswitch:
op1 *= op2;
//printf("SMLA_INST:BB,op1=0x%x, op2=0x%x. Rn=0x%x\n", op1, op2, Rn);
if (AddOverflow(op1, Rn, op1 + Rn))
- SETS;
+ SETQ;
state->Reg[BITS (16, 19)] = op1 + Rn;
break;
}
@@ -1682,7 +1682,7 @@ mainswitch:
ARMword result = op1 + op2;
if (AddOverflow(op1, op2, result)) {
result = POS (result) ? 0x80000000 : 0x7fffffff;
- SETS;
+ SETQ;
}
state->Reg[BITS (12, 15)] = result;
break;
@@ -1724,7 +1724,7 @@ mainswitch:
TAKEABORT;
} else if ((BITS (0, 11) == 0) && (LHSReg == 15)) { /* MRS CPSR */
UNDEF_MRSPC;
- DEST = ECC | EINT | EMODE;
+ DEST = ARMul_GetCPSR(state);
} else {
UNDEF_Test;
}
@@ -1795,7 +1795,7 @@ mainswitch:
ARMword Rn = state->Reg[BITS(12, 15)];
if (AddOverflow((ARMword)result, Rn, (ARMword)(result + Rn)))
- SETS;
+ SETQ;
result += Rn;
}
state->Reg[BITS (16, 19)] = (ARMword)result;
@@ -1811,7 +1811,7 @@ mainswitch:
if (SubOverflow
(op1, op2, result)) {
result = POS (result) ? 0x80000000 : 0x7fffffff;
- SETS;
+ SETQ;
}
state->Reg[BITS (12, 15)] = result;
@@ -1934,13 +1934,13 @@ mainswitch:
if (AddOverflow
(op2, op2, op2d)) {
- SETS;
+ SETQ;
op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
}
result = op1 + op2d;
if (AddOverflow(op1, op2d, result)) {
- SETS;
+ SETQ;
result = POS (result) ? 0x80000000 : 0x7fffffff;
}
@@ -2053,13 +2053,13 @@ mainswitch:
ARMword result;
if (AddOverflow(op2, op2, op2d)) {
- SETS;
+ SETQ;
op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
}
result = op1 - op2d;
if (SubOverflow(op1, op2d, result)) {
- SETS;
+ SETQ;
result = POS (result) ? 0x80000000 : 0x7fffffff;
}
@@ -5877,6 +5877,8 @@ L_stm_s_takeabort:
state->Cpsr &= ~(1 << 18);
state->Cpsr &= ~(1 << 19);
}
+
+ ARMul_CPSRAltered(state);
return 1;
}
// SADD8/SSUB8
@@ -5948,6 +5950,7 @@ L_stm_s_takeabort:
state->Cpsr &= ~(1 << 19);
}
+ ARMul_CPSRAltered(state);
state->Reg[rd_idx] = (lo_val1 | lo_val2 << 8 | hi_val1 << 16 | hi_val2 << 24);
return 1;
}
@@ -6024,15 +6027,33 @@ L_stm_s_takeabort:
if ((instr & 0x0F0) == 0x070) { // USUB16
h1 = ((u16)from - (u16)to);
h2 = ((u16)(from >> 16) - (u16)(to >> 16));
- if (!(h1 & 0xffff0000)) state->Cpsr |= (3 << 16);
- if (!(h2 & 0xffff0000)) state->Cpsr |= (3 << 18);
+
+ if (!(h1 & 0xffff0000))
+ state->Cpsr |= (3 << 16);
+ else
+ state->Cpsr &= ~(3 << 16);
+
+ if (!(h2 & 0xffff0000))
+ state->Cpsr |= (3 << 18);
+ else
+ state->Cpsr &= ~(3 << 18);
}
else { // UADD16
h1 = ((u16)from + (u16)to);
h2 = ((u16)(from >> 16) + (u16)(to >> 16));
- if (h1 & 0xffff0000) state->Cpsr |= (3 << 16);
- if (h2 & 0xffff0000) state->Cpsr |= (3 << 18);
+
+ if (h1 & 0xffff0000)
+ state->Cpsr |= (3 << 16);
+ else
+ state->Cpsr &= ~(3 << 16);
+
+ if (h2 & 0xffff0000)
+ state->Cpsr |= (3 << 18);
+ else
+ state->Cpsr &= ~(3 << 18);
}
+
+ ARMul_CPSRAltered(state);
state->Reg[rd] = (u32)((h1 & 0xffff) | ((h2 & 0xffff) << 16));
return 1;
}
@@ -6045,10 +6066,26 @@ L_stm_s_takeabort:
b2 = ((u8)(from >> 8) - (u8)(to >> 8));
b3 = ((u8)(from >> 16) - (u8)(to >> 16));
b4 = ((u8)(from >> 24) - (u8)(to >> 24));
- if (!(b1 & 0xffffff00)) state->Cpsr |= (1 << 16);
- if (!(b2 & 0xffffff00)) state->Cpsr |= (1 << 17);
- if (!(b3 & 0xffffff00)) state->Cpsr |= (1 << 18);
- if (!(b4 & 0xffffff00)) state->Cpsr |= (1 << 19);
+
+ if (!(b1 & 0xffffff00))
+ state->Cpsr |= (1 << 16);
+ else
+ state->Cpsr &= ~(1 << 16);
+
+ if (!(b2 & 0xffffff00))
+ state->Cpsr |= (1 << 17);
+ else
+ state->Cpsr &= ~(1 << 17);
+
+ if (!(b3 & 0xffffff00))
+ state->Cpsr |= (1 << 18);
+ else
+ state->Cpsr &= ~(1 << 18);
+
+ if (!(b4 & 0xffffff00))
+ state->Cpsr |= (1 << 19);
+ else
+ state->Cpsr &= ~(1 << 19);
}
else { // UADD8
b1 = ((u8)from + (u8)to);
@@ -6071,13 +6108,13 @@ L_stm_s_takeabort:
else
state->Cpsr &= ~(1 << 18);
-
if (b4 & 0xffffff00)
state->Cpsr |= (1 << 19);
else
state->Cpsr &= ~(1 << 19);
}
+ ARMul_CPSRAltered(state);
state->Reg[rd] = (u32)(b1 | (b2 & 0xff) << 8 | (b3 & 0xff) << 16 | (b4 & 0xff) << 24);
return 1;
}
@@ -6116,7 +6153,7 @@ L_stm_s_takeabort:
u32 rm = (instr >> 0) & 0xF;
u32 from = state->Reg[rn];
u32 to = state->Reg[rm];
- u32 cpsr = state->Cpsr;
+ u32 cpsr = ARMul_GetCPSR(state);
if ((instr & 0xFF0) == 0xFB0) { // SEL
u32 result;
if (cpsr & (1 << 16))
@@ -6172,16 +6209,23 @@ L_stm_s_takeabort:
s16 rn_lo = (state->Reg[rn_idx]);
s16 rn_hi = (state->Reg[rn_idx] >> 16);
- if (rn_lo > max)
+ if (rn_lo > max) {
rn_lo = max;
- else if (rn_lo < min)
+ state->Cpsr |= (1 << 27);
+ } else if (rn_lo < min) {
rn_lo = min;
+ state->Cpsr |= (1 << 27);
+ }
- if (rn_hi > max)
+ if (rn_hi > max) {
rn_hi = max;
- else if (rn_hi < min)
+ state->Cpsr |= (1 << 27);
+ } else if (rn_hi < min) {
rn_hi = min;
+ state->Cpsr |= (1 << 27);
+ }
+ ARMul_CPSRAltered(state);
state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi & 0xFFFF) << 16);
return 1;
}
@@ -6313,16 +6357,23 @@ L_stm_s_takeabort:
s16 rn_lo = (state->Reg[rn_idx]);
s16 rn_hi = (state->Reg[rn_idx] >> 16);
- if (max < rn_lo)
+ if (max < rn_lo) {
rn_lo = max;
- else if (rn_lo < 0)
+ state->Cpsr |= (1 << 27);
+ } else if (rn_lo < 0) {
rn_lo = 0;
+ state->Cpsr |= (1 << 27);
+ }
- if (max < rn_hi)
+ if (max < rn_hi) {
rn_hi = max;
- else if (rn_hi < 0)
+ state->Cpsr |= (1 << 27);
+ } else if (rn_hi < 0) {
rn_hi = 0;
-
+ state->Cpsr |= (1 << 27);
+ }
+
+ ARMul_CPSRAltered(state);
state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi << 16) & 0xFFFF);
return 1;
}
@@ -6427,22 +6478,28 @@ L_stm_s_takeabort:
const s16 rn_lo = (rn_val & 0xFFFF);
const s16 rn_hi = ((rn_val >> 16) & 0xFFFF);
- // SMUAD
- if ((instr & 0xf0d0) == 0xf010) {
- state->Reg[rd_idx] = (rn_lo * rm_lo) + (rn_hi * rm_hi);
- }
- // SMUSD
- else if ((instr & 0xf0d0) == 0xf050) {
- state->Reg[rd_idx] = (rn_lo * rm_lo) - (rn_hi * rm_hi);
- }
- // SMLAD
- else if ((instr & 0xd0) == 0x10) {
- state->Reg[rd_idx] = (rn_lo * rm_lo) + (rn_hi * rm_hi) + (s32)state->Reg[ra_idx];
+ const u32 product1 = (rn_lo * rm_lo);
+ const u32 product2 = (rn_hi * rm_hi);
+
+ // SMUAD and SMLAD
+ if (BIT(6) == 0) {
+ state->Reg[rd_idx] = product1 + product2;
+
+ if (BITS(12, 15) != 15) {
+ state->Reg[rd_idx] += state->Reg[ra_idx];
+ ARMul_AddOverflowQ(state, product1 + product2, state->Reg[ra_idx]);
+ }
+
+ ARMul_AddOverflowQ(state, product1, product2);
}
- // SMLSD
+ // SMUSD and SMLSD
else {
- state->Reg[rd_idx] = ((rn_lo * rm_lo) - (rn_hi * rm_hi)) + (s32)state->Reg[ra_idx];
+ state->Reg[rd_idx] = product1 - product2;
+
+ if (BITS(12, 15) != 15)
+ state->Reg[rd_idx] += state->Reg[ra_idx];
}
+
return 1;
}
break;
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 00:27:41 +0200