diff options
Diffstat (limited to '')
-rw-r--r-- | src/core/arm/dyncom/arm_dyncom.h | 5 | ||||
-rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 13 | ||||
-rw-r--r-- | src/core/arm/dyncom/arm_dyncom_thumb.cpp | 14 |
3 files changed, 17 insertions, 15 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom.h b/src/core/arm/dyncom/arm_dyncom.h index 2488c879c..cc9355722 100644 --- a/src/core/arm/dyncom/arm_dyncom.h +++ b/src/core/arm/dyncom/arm_dyncom.h @@ -10,6 +10,11 @@ #include "core/arm/arm_interface.h" #include "core/arm/skyeye_common/armdefs.h" +#include "core/arm/skyeye_common/arm_regformat.h" + +namespace Core { +struct ThreadContext; +} class ARM_DynCom final : virtual public ARM_Interface { public: diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index b00eb49a9..785f39566 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -4144,11 +4144,13 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { bx_inst* const inst_cream = (bx_inst*)inst_base->component; + u32 address = RM; + if (inst_cream->Rm == 15) - LOG_WARNING(Core_ARM11, "BX at pc %x: use of Rm = R15 is discouraged", cpu->Reg[15]); + address += 2 * GET_INST_SIZE(cpu); - cpu->TFlag = cpu->Reg[inst_cream->Rm] & 0x1; - cpu->Reg[15] = cpu->Reg[inst_cream->Rm] & 0xfffffffe; + cpu->TFlag = address & 1; + cpu->Reg[15] = address & 0xfffffffe; INC_PC(sizeof(bx_inst)); goto DISPATCH; } @@ -5695,7 +5697,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { const s16 operand2 = (high) ? ((rm_val >> 16) & 0xFFFF) : (rm_val & 0xFFFF); const s64 result = (s64)(s32)rn_val * (s64)(s32)operand2 + ((s64)(s32)ra_val << 16); - RD = (result & (0xFFFFFFFFFFFFFFFFLL >> 15)) >> 16; + RD = BITS(result, 16, 47); if ((result >> 16) != (s32)RD) cpu->Cpsr |= (1 << 27); @@ -6246,7 +6248,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { SWI_INST: { if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { - SVC::CallSVC(Memory::Read32(cpu->Reg[15])); + swi_inst* const inst_cream = (swi_inst*)inst_base->component; + SVC::CallSVC(inst_cream->num & 0xFFFF); } cpu->Reg[15] += GET_INST_SIZE(cpu); diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp index 3e79c44c0..f10a5b70f 100644 --- a/src/core/arm/dyncom/arm_dyncom_thumb.cpp +++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp @@ -130,14 +130,13 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) { } } else { ARMword Rd = ((tinstr & 0x0007) >> 0); - ARMword Rs = ((tinstr & 0x0038) >> 3); + ARMword Rs = ((tinstr & 0x0078) >> 3); if (tinstr & (1 << 7)) Rd += 8; - if (tinstr & (1 << 6)) - Rs += 8; switch ((tinstr & 0x03C0) >> 6) { + case 0x0: // ADD Rd,Rd,Rs case 0x1: // ADD Rd,Rd,Hs case 0x2: // ADD Hd,Hd,Rs case 0x3: // ADD Hd,Hd,Hs @@ -146,19 +145,19 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) { |(Rd << 12) // Rd |(Rs << 0); // Rm break; + case 0x4: // CMP Rd,Rs case 0x5: // CMP Rd,Hs case 0x6: // CMP Hd,Rs case 0x7: // CMP Hd,Hs *ainstr = 0xE1500000 // base | (Rd << 16) // Rn - |(Rd << 12) // Rd |(Rs << 0); // Rm break; + case 0x8: // MOV Rd,Rs case 0x9: // MOV Rd,Hs case 0xA: // MOV Hd,Rs case 0xB: // MOV Hd,Hs *ainstr = 0xE1A00000 // base - | (Rd << 16) // Rn |(Rd << 12) // Rd |(Rs << 0); // Rm break; @@ -167,11 +166,6 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) { *ainstr = 0xE12FFF10 // base | ((tinstr & 0x0078) >> 3); // Rd break; - case 0x0: // UNDEFINED - case 0x4: // UNDEFINED - case 0x8: // UNDEFINED - valid = t_undefined; - break; case 0xE: // BLX case 0xF: // BLX *ainstr = 0xE1200030 // base |