diff options
Diffstat (limited to 'src/core/arm/dynarmic/arm_dynarmic_32.cpp')
-rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_32.cpp | 327 |
1 files changed, 155 insertions, 172 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.cpp b/src/core/arm/dynarmic/arm_dynarmic_32.cpp index 44a297cdc..cf52c0505 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_32.cpp +++ b/src/core/arm/dynarmic/arm_dynarmic_32.cpp @@ -1,25 +1,13 @@ // SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project // SPDX-License-Identifier: GPL-2.0-or-later -#include <cinttypes> -#include <memory> -#include <dynarmic/interface/A32/a32.h> -#include <dynarmic/interface/A32/config.h> -#include "common/assert.h" -#include "common/literals.h" -#include "common/logging/log.h" -#include "common/page_table.h" #include "common/settings.h" #include "core/arm/dynarmic/arm_dynarmic.h" #include "core/arm/dynarmic/arm_dynarmic_32.h" #include "core/arm/dynarmic/dynarmic_cp15.h" #include "core/arm/dynarmic/dynarmic_exclusive_monitor.h" -#include "core/core.h" #include "core/core_timing.h" -#include "core/debugger/debugger.h" #include "core/hle/kernel/k_process.h" -#include "core/hle/kernel/svc.h" -#include "core/memory.h" namespace Core { @@ -27,78 +15,78 @@ using namespace Common::Literals; class DynarmicCallbacks32 : public Dynarmic::A32::UserCallbacks { public: - explicit DynarmicCallbacks32(ARM_Dynarmic_32& parent_) - : parent{parent_}, memory(parent.system.ApplicationMemory()), - debugger_enabled{parent.system.DebuggerEnabled()}, - check_memory_access{debugger_enabled || - !Settings::values.cpuopt_ignore_memory_aborts.GetValue()} {} + explicit DynarmicCallbacks32(ArmDynarmic32& parent, const Kernel::KProcess* process) + : m_parent{parent}, m_memory(process->GetMemory()), + m_process(process), m_debugger_enabled{parent.m_system.DebuggerEnabled()}, + m_check_memory_access{m_debugger_enabled || + !Settings::values.cpuopt_ignore_memory_aborts.GetValue()} {} u8 MemoryRead8(u32 vaddr) override { CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Read); - return memory.Read8(vaddr); + return m_memory.Read8(vaddr); } u16 MemoryRead16(u32 vaddr) override { CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Read); - return memory.Read16(vaddr); + return m_memory.Read16(vaddr); } u32 MemoryRead32(u32 vaddr) override { CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Read); - return memory.Read32(vaddr); + return m_memory.Read32(vaddr); } u64 MemoryRead64(u32 vaddr) override { CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Read); - return memory.Read64(vaddr); + return m_memory.Read64(vaddr); } std::optional<u32> MemoryReadCode(u32 vaddr) override { - if (!memory.IsValidVirtualAddressRange(vaddr, sizeof(u32))) { + if (!m_memory.IsValidVirtualAddressRange(vaddr, sizeof(u32))) { return std::nullopt; } - return memory.Read32(vaddr); + return m_memory.Read32(vaddr); } void MemoryWrite8(u32 vaddr, u8 value) override { if (CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Write)) { - memory.Write8(vaddr, value); + m_memory.Write8(vaddr, value); } } void MemoryWrite16(u32 vaddr, u16 value) override { if (CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Write)) { - memory.Write16(vaddr, value); + m_memory.Write16(vaddr, value); } } void MemoryWrite32(u32 vaddr, u32 value) override { if (CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Write)) { - memory.Write32(vaddr, value); + m_memory.Write32(vaddr, value); } } void MemoryWrite64(u32 vaddr, u64 value) override { if (CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Write)) { - memory.Write64(vaddr, value); + m_memory.Write64(vaddr, value); } } bool MemoryWriteExclusive8(u32 vaddr, u8 value, u8 expected) override { return CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Write) && - memory.WriteExclusive8(vaddr, value, expected); + m_memory.WriteExclusive8(vaddr, value, expected); } bool MemoryWriteExclusive16(u32 vaddr, u16 value, u16 expected) override { return CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Write) && - memory.WriteExclusive16(vaddr, value, expected); + m_memory.WriteExclusive16(vaddr, value, expected); } bool MemoryWriteExclusive32(u32 vaddr, u32 value, u32 expected) override { return CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Write) && - memory.WriteExclusive32(vaddr, value, expected); + m_memory.WriteExclusive32(vaddr, value, expected); } bool MemoryWriteExclusive64(u32 vaddr, u64 value, u64 expected) override { return CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Write) && - memory.WriteExclusive64(vaddr, value, expected); + m_memory.WriteExclusive64(vaddr, value, expected); } void InterpreterFallback(u32 pc, std::size_t num_instructions) override { - parent.LogBacktrace(); + m_parent.LogBacktrace(m_process); LOG_ERROR(Core_ARM, "Unimplemented instruction @ 0x{:X} for {} instructions (instr = {:08X})", pc, - num_instructions, memory.Read32(pc)); + num_instructions, m_memory.Read32(pc)); } void ExceptionRaised(u32 pc, Dynarmic::A32::Exception exception) override { @@ -108,73 +96,64 @@ public: ReturnException(pc, PrefetchAbort); return; default: - if (debugger_enabled) { + if (m_debugger_enabled) { ReturnException(pc, InstructionBreakpoint); return; } - parent.LogBacktrace(); + m_parent.LogBacktrace(m_process); LOG_CRITICAL(Core_ARM, "ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X}, thumb = {})", - exception, pc, memory.Read32(pc), parent.IsInThumbMode()); + exception, pc, m_memory.Read32(pc), m_parent.IsInThumbMode()); } } void CallSVC(u32 swi) override { - parent.svc_swi = swi; - parent.jit.load()->HaltExecution(SupervisorCall); + m_parent.m_svc_swi = swi; + m_parent.m_jit->HaltExecution(SupervisorCall); } void AddTicks(u64 ticks) override { - if (parent.uses_wall_clock) { - return; - } + ASSERT_MSG(!m_parent.m_uses_wall_clock, "Dynarmic ticking disabled"); // Divide the number of ticks by the amount of CPU cores. TODO(Subv): This yields only a // rough approximation of the amount of executed ticks in the system, it may be thrown off // if not all cores are doing a similar amount of work. Instead of doing this, we should // device a way so that timing is consistent across all cores without increasing the ticks 4 // times. - u64 amortized_ticks = - (ticks - num_interpreted_instructions) / Core::Hardware::NUM_CPU_CORES; + u64 amortized_ticks = ticks / Core::Hardware::NUM_CPU_CORES; // Always execute at least one tick. amortized_ticks = std::max<u64>(amortized_ticks, 1); - parent.system.CoreTiming().AddTicks(amortized_ticks); - num_interpreted_instructions = 0; + m_parent.m_system.CoreTiming().AddTicks(amortized_ticks); } u64 GetTicksRemaining() override { - if (parent.uses_wall_clock) { - if (!IsInterrupted()) { - return minimum_run_cycles; - } - return 0U; - } + ASSERT_MSG(!m_parent.m_uses_wall_clock, "Dynarmic ticking disabled"); - return std::max<s64>(parent.system.CoreTiming().GetDowncount(), 0); + return std::max<s64>(m_parent.m_system.CoreTiming().GetDowncount(), 0); } bool CheckMemoryAccess(u64 addr, u64 size, Kernel::DebugWatchpointType type) { - if (!check_memory_access) { + if (!m_check_memory_access) { return true; } - if (!memory.IsValidVirtualAddressRange(addr, size)) { + if (!m_memory.IsValidVirtualAddressRange(addr, size)) { LOG_CRITICAL(Core_ARM, "Stopping execution due to unmapped memory access at {:#x}", addr); - parent.jit.load()->HaltExecution(PrefetchAbort); + m_parent.m_jit->HaltExecution(PrefetchAbort); return false; } - if (!debugger_enabled) { + if (!m_debugger_enabled) { return true; } - const auto match{parent.MatchingWatchpoint(addr, size, type)}; + const auto match{m_parent.MatchingWatchpoint(addr, size, type)}; if (match) { - parent.halted_watchpoint = match; - parent.jit.load()->HaltExecution(DataAbort); + m_parent.m_halted_watchpoint = match; + m_parent.m_jit->HaltExecution(DataAbort); return false; } @@ -182,32 +161,31 @@ public: } void ReturnException(u32 pc, Dynarmic::HaltReason hr) { - parent.SaveContext(parent.breakpoint_context); - parent.breakpoint_context.cpu_registers[15] = pc; - parent.jit.load()->HaltExecution(hr); + m_parent.GetContext(m_parent.m_breakpoint_context); + m_parent.m_breakpoint_context.pc = pc; + m_parent.m_breakpoint_context.r[15] = pc; + m_parent.m_jit->HaltExecution(hr); } - bool IsInterrupted() { - return parent.system.Kernel().PhysicalCore(parent.core_index).IsInterrupted(); - } - - ARM_Dynarmic_32& parent; - Core::Memory::Memory& memory; - std::size_t num_interpreted_instructions{}; - const bool debugger_enabled{}; - const bool check_memory_access{}; - static constexpr u64 minimum_run_cycles = 10000U; + ArmDynarmic32& m_parent; + Core::Memory::Memory& m_memory; + const Kernel::KProcess* m_process{}; + const bool m_debugger_enabled{}; + const bool m_check_memory_access{}; + static constexpr u64 MinimumRunCycles = 10000U; }; -std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable* page_table) const { +std::shared_ptr<Dynarmic::A32::Jit> ArmDynarmic32::MakeJit(Common::PageTable* page_table) const { Dynarmic::A32::UserConfig config; - config.callbacks = cb.get(); - config.coprocessors[15] = cp15; + config.callbacks = m_cb.get(); + config.coprocessors[15] = m_cp15; config.define_unpredictable_behaviour = true; - static constexpr std::size_t YUZU_PAGEBITS = 12; - static constexpr std::size_t NUM_PAGE_TABLE_ENTRIES = 1 << (32 - YUZU_PAGEBITS); + if (page_table) { - config.page_table = reinterpret_cast<std::array<std::uint8_t*, NUM_PAGE_TABLE_ENTRIES>*>( + constexpr size_t PageBits = 12; + constexpr size_t NumPageTableEntries = 1 << (32 - PageBits); + + config.page_table = reinterpret_cast<std::array<std::uint8_t*, NumPageTableEntries>*>( page_table->pointers.data()); config.absolute_offset_page_table = true; config.page_table_pointer_mask_bits = Common::PageTable::ATTRIBUTE_BITS; @@ -221,12 +199,12 @@ std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable* } // Multi-process state - config.processor_id = core_index; - config.global_monitor = &exclusive_monitor.monitor; + config.processor_id = m_core_index; + config.global_monitor = &m_exclusive_monitor.monitor; // Timing - config.wall_clock_cntpct = uses_wall_clock; - config.enable_cycle_counting = true; + config.wall_clock_cntpct = m_uses_wall_clock; + config.enable_cycle_counting = !m_uses_wall_clock; // Code cache size #ifdef ARCHITECTURE_arm64 @@ -236,7 +214,7 @@ std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable* #endif // Allow memory fault handling to work - if (system.DebuggerEnabled()) { + if (m_system.DebuggerEnabled()) { config.check_halt_on_memory_access = true; } @@ -325,137 +303,142 @@ std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable* return std::make_unique<Dynarmic::A32::Jit>(config); } -HaltReason ARM_Dynarmic_32::RunJit() { - return TranslateHaltReason(jit.load()->Run()); +static std::pair<u32, u32> FpscrToFpsrFpcr(u32 fpscr) { + // FPSCR bits [31:27] are mapped to FPSR[31:27]. + // FPSCR bit [7] is mapped to FPSR[7]. + // FPSCR bits [4:0] are mapped to FPSR[4:0]. + const u32 nzcv = fpscr & 0xf8000000; + const u32 idc = fpscr & 0x80; + const u32 fiq = fpscr & 0x1f; + const u32 fpsr = nzcv | idc | fiq; + + // FPSCR bits [26:15] are mapped to FPCR[26:15]. + // FPSCR bits [12:8] are mapped to FPCR[12:8]. + const u32 round = fpscr & 0x7ff8000; + const u32 trap = fpscr & 0x1f00; + const u32 fpcr = round | trap; + + return {fpsr, fpcr}; } -HaltReason ARM_Dynarmic_32::StepJit() { - return TranslateHaltReason(jit.load()->Step()); +static u32 FpsrFpcrToFpscr(u64 fpsr, u64 fpcr) { + auto [s, c] = FpscrToFpsrFpcr(static_cast<u32>(fpsr | fpcr)); + return s | c; } -u32 ARM_Dynarmic_32::GetSvcNumber() const { - return svc_swi; +bool ArmDynarmic32::IsInThumbMode() const { + return (m_jit->Cpsr() & 0x20) != 0; } -const Kernel::DebugWatchpoint* ARM_Dynarmic_32::HaltedWatchpoint() const { - return halted_watchpoint; +HaltReason ArmDynarmic32::RunThread(Kernel::KThread* thread) { + m_jit->ClearExclusiveState(); + return TranslateHaltReason(m_jit->Run()); } -void ARM_Dynarmic_32::RewindBreakpointInstruction() { - LoadContext(breakpoint_context); +HaltReason ArmDynarmic32::StepThread(Kernel::KThread* thread) { + m_jit->ClearExclusiveState(); + return TranslateHaltReason(m_jit->Step()); } -ARM_Dynarmic_32::ARM_Dynarmic_32(System& system_, bool uses_wall_clock_, - DynarmicExclusiveMonitor& exclusive_monitor_, - std::size_t core_index_) - : ARM_Interface{system_, uses_wall_clock_}, cb(std::make_unique<DynarmicCallbacks32>(*this)), - cp15(std::make_shared<DynarmicCP15>(*this)), core_index{core_index_}, - exclusive_monitor{exclusive_monitor_}, null_jit{MakeJit(nullptr)}, jit{null_jit.get()} {} +u32 ArmDynarmic32::GetSvcNumber() const { + return m_svc_swi; +} -ARM_Dynarmic_32::~ARM_Dynarmic_32() = default; +void ArmDynarmic32::GetSvcArguments(std::span<uint64_t, 8> args) const { + Dynarmic::A32::Jit& j = *m_jit; + auto& gpr = j.Regs(); -void ARM_Dynarmic_32::SetPC(u64 pc) { - jit.load()->Regs()[15] = static_cast<u32>(pc); + for (size_t i = 0; i < 8; i++) { + args[i] = gpr[i]; + } } -u64 ARM_Dynarmic_32::GetPC() const { - return jit.load()->Regs()[15]; -} +void ArmDynarmic32::SetSvcArguments(std::span<const uint64_t, 8> args) { + Dynarmic::A32::Jit& j = *m_jit; + auto& gpr = j.Regs(); -u64 ARM_Dynarmic_32::GetSP() const { - return jit.load()->Regs()[13]; + for (size_t i = 0; i < 8; i++) { + gpr[i] = static_cast<u32>(args[i]); + } } -u64 ARM_Dynarmic_32::GetReg(int index) const { - return jit.load()->Regs()[index]; +const Kernel::DebugWatchpoint* ArmDynarmic32::HaltedWatchpoint() const { + return m_halted_watchpoint; } -void ARM_Dynarmic_32::SetReg(int index, u64 value) { - jit.load()->Regs()[index] = static_cast<u32>(value); +void ArmDynarmic32::RewindBreakpointInstruction() { + this->SetContext(m_breakpoint_context); } -u128 ARM_Dynarmic_32::GetVectorReg(int index) const { - return {}; +ArmDynarmic32::ArmDynarmic32(System& system, bool uses_wall_clock, const Kernel::KProcess* process, + DynarmicExclusiveMonitor& exclusive_monitor, std::size_t core_index) + : ArmInterface{uses_wall_clock}, m_system{system}, m_exclusive_monitor{exclusive_monitor}, + m_cb(std::make_unique<DynarmicCallbacks32>(*this, process)), + m_cp15(std::make_shared<DynarmicCP15>(*this)), m_core_index{core_index} { + auto& page_table_impl = process->GetPageTable().GetBasePageTable().GetImpl(); + m_jit = MakeJit(&page_table_impl); } -void ARM_Dynarmic_32::SetVectorReg(int index, u128 value) {} +ArmDynarmic32::~ArmDynarmic32() = default; -u32 ARM_Dynarmic_32::GetPSTATE() const { - return jit.load()->Cpsr(); +void ArmDynarmic32::SetTpidrroEl0(u64 value) { + m_cp15->uro = static_cast<u32>(value); } -void ARM_Dynarmic_32::SetPSTATE(u32 cpsr) { - jit.load()->SetCpsr(cpsr); -} +void ArmDynarmic32::GetContext(Kernel::Svc::ThreadContext& ctx) const { + Dynarmic::A32::Jit& j = *m_jit; + auto& gpr = j.Regs(); + auto& fpr = j.ExtRegs(); -u64 ARM_Dynarmic_32::GetTlsAddress() const { - return cp15->uro; -} + for (size_t i = 0; i < 16; i++) { + ctx.r[i] = gpr[i]; + } -void ARM_Dynarmic_32::SetTlsAddress(u64 address) { - cp15->uro = static_cast<u32>(address); -} + ctx.fp = gpr[11]; + ctx.sp = gpr[13]; + ctx.lr = gpr[14]; + ctx.pc = gpr[15]; + ctx.pstate = j.Cpsr(); -u64 ARM_Dynarmic_32::GetTPIDR_EL0() const { - return cp15->uprw; -} + for (size_t i = 0; i < 32; i++) { + ctx.v[i] = {fpr[i], 0}; + } -void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) { - cp15->uprw = static_cast<u32>(value); + auto [fpsr, fpcr] = FpscrToFpsrFpcr(j.Fpscr()); + ctx.fpcr = fpcr; + ctx.fpsr = fpsr; + ctx.tpidr = m_cp15->uprw; } -void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) const { - Dynarmic::A32::Jit* j = jit.load(); - ctx.cpu_registers = j->Regs(); - ctx.extension_registers = j->ExtRegs(); - ctx.cpsr = j->Cpsr(); - ctx.fpscr = j->Fpscr(); -} +void ArmDynarmic32::SetContext(const Kernel::Svc::ThreadContext& ctx) { + Dynarmic::A32::Jit& j = *m_jit; + auto& gpr = j.Regs(); + auto& fpr = j.ExtRegs(); -void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) { - Dynarmic::A32::Jit* j = jit.load(); - j->Regs() = ctx.cpu_registers; - j->ExtRegs() = ctx.extension_registers; - j->SetCpsr(ctx.cpsr); - j->SetFpscr(ctx.fpscr); -} + for (size_t i = 0; i < 16; i++) { + gpr[i] = static_cast<u32>(ctx.r[i]); + } -void ARM_Dynarmic_32::SignalInterrupt() { - jit.load()->HaltExecution(BreakLoop); -} + j.SetCpsr(ctx.pstate); -void ARM_Dynarmic_32::ClearInterrupt() { - jit.load()->ClearHalt(BreakLoop); -} + for (size_t i = 0; i < 32; i++) { + fpr[i] = static_cast<u32>(ctx.v[i][0]); + } -void ARM_Dynarmic_32::ClearInstructionCache() { - jit.load()->ClearCache(); + j.SetFpscr(FpsrFpcrToFpscr(ctx.fpsr, ctx.fpcr)); + m_cp15->uprw = static_cast<u32>(ctx.tpidr); } -void ARM_Dynarmic_32::InvalidateCacheRange(u64 addr, std::size_t size) { - jit.load()->InvalidateCacheRange(static_cast<u32>(addr), size); +void ArmDynarmic32::SignalInterrupt(Kernel::KThread* thread) { + m_jit->HaltExecution(BreakLoop); } -void ARM_Dynarmic_32::ClearExclusiveState() { - jit.load()->ClearExclusiveState(); +void ArmDynarmic32::ClearInstructionCache() { + m_jit->ClearCache(); } -void ARM_Dynarmic_32::PageTableChanged(Common::PageTable& page_table, - std::size_t new_address_space_size_in_bits) { - ThreadContext32 ctx{}; - SaveContext(ctx); - - auto key = std::make_pair(&page_table, new_address_space_size_in_bits); - auto iter = jit_cache.find(key); - if (iter != jit_cache.end()) { - jit.store(iter->second.get()); - LoadContext(ctx); - return; - } - std::shared_ptr new_jit = MakeJit(&page_table); - jit.store(new_jit.get()); - LoadContext(ctx); - jit_cache.emplace(key, std::move(new_jit)); +void ArmDynarmic32::InvalidateCacheRange(u64 addr, std::size_t size) { + m_jit->InvalidateCacheRange(static_cast<u32>(addr), size); } } // namespace Core |