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-rw-r--r--appveyor.yml2
-rw-r--r--src/video_core/engines/shader_bytecode.h42
-rw-r--r--src/video_core/renderer_opengl/gl_shader_decompiler.cpp80
3 files changed, 108 insertions, 16 deletions
diff --git a/appveyor.yml b/appveyor.yml
index 4f928adb5..72cda26a7 100644
--- a/appveyor.yml
+++ b/appveyor.yml
@@ -53,7 +53,7 @@ build_script:
# https://www.appveyor.com/docs/build-phase
msbuild msvc_build/yuzu.sln /maxcpucount /logger:"C:\Program Files\AppVeyor\BuildAgent\Appveyor.MSBuildLogger.dll"
} else {
- C:\msys64\usr\bin\bash.exe -lc 'mingw32-make -j4 -C mingw_build/ 2>&1'
+ C:\msys64\usr\bin\bash.exe -lc 'mingw32-make -C mingw_build/ 2>&1'
}
after_build:
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index 93654eb66..4eb507325 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -237,9 +237,22 @@ union Instruction {
std::memcpy(&result, &imm, sizeof(imm));
return result;
}
+
+ s32 GetSignedImm20_20() const {
+ u32 immediate = static_cast<u32>(imm20_19 | (negate_imm << 19));
+ // Sign extend the 20-bit value.
+ u32 mask = 1U << (20 - 1);
+ return static_cast<s32>((immediate ^ mask) - mask);
+ }
} alu;
union {
+ BitField<39, 5, u64> shift_amount;
+ BitField<48, 1, u64> negate_b;
+ BitField<49, 1, u64> negate_a;
+ } iscadd;
+
+ union {
BitField<48, 1, u64> negate_b;
BitField<49, 1, u64> negate_c;
} ffma;
@@ -328,15 +341,16 @@ union Instruction {
} texs;
union {
- BitField<20, 5, u64> target;
+ BitField<20, 24, u64> target;
BitField<5, 1, u64> constant_buffer;
s32 GetBranchTarget() const {
// Sign extend the branch target offset
- u32 mask = 1U << (5 - 1);
+ u32 mask = 1U << (24 - 1);
u32 value = static_cast<u32>(target);
- // The branch offset is relative to the next instruction, so add 1 to it.
- return static_cast<s32>((value ^ mask) - mask) + 1;
+ // The branch offset is relative to the next instruction and is stored in bytes, so
+ // divide it by the size of an instruction and add 1 to it.
+ return static_cast<s32>((value ^ mask) - mask) / sizeof(Instruction) + 1;
}
} bra;
@@ -378,6 +392,9 @@ public:
FMUL_R,
FMUL_IMM,
FMUL32_IMM,
+ ISCADD_C, // Scale and Add
+ ISCADD_R,
+ ISCADD_IMM,
MUFU, // Multi-Function Operator
RRO_C, // Range Reduction Operator
RRO_R,
@@ -399,6 +416,9 @@ public:
MOV_R,
MOV_IMM,
MOV32_IMM,
+ SHL_C,
+ SHL_R,
+ SHL_IMM,
SHR_C,
SHR_R,
SHR_IMM,
@@ -421,6 +441,8 @@ public:
Trivial,
Arithmetic,
Logic,
+ Shift,
+ ScaledAdd,
Ffma,
Flow,
Memory,
@@ -544,6 +566,9 @@ private:
INST("0101110001101---", Id::FMUL_R, Type::Arithmetic, "FMUL_R"),
INST("0011100-01101---", Id::FMUL_IMM, Type::Arithmetic, "FMUL_IMM"),
INST("00011110--------", Id::FMUL32_IMM, Type::Arithmetic, "FMUL32_IMM"),
+ INST("0100110000011---", Id::ISCADD_C, Type::ScaledAdd, "ISCADD_C"),
+ INST("0101110000011---", Id::ISCADD_R, Type::ScaledAdd, "ISCADD_R"),
+ INST("0011100-00011---", Id::ISCADD_IMM, Type::ScaledAdd, "ISCADD_IMM"),
INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
@@ -558,13 +583,16 @@ private:
INST("0101110010011---", Id::MOV_R, Type::Arithmetic, "MOV_R"),
INST("0011100-10011---", Id::MOV_IMM, Type::Arithmetic, "MOV_IMM"),
INST("000000010000----", Id::MOV32_IMM, Type::Arithmetic, "MOV32_IMM"),
- INST("0100110000101---", Id::SHR_C, Type::Arithmetic, "SHR_C"),
- INST("0101110000101---", Id::SHR_R, Type::Arithmetic, "SHR_R"),
- INST("0011100-00101---", Id::SHR_IMM, Type::Arithmetic, "SHR_IMM"),
INST("0100110001100---", Id::FMNMX_C, Type::Arithmetic, "FMNMX_C"),
INST("0101110001100---", Id::FMNMX_R, Type::Arithmetic, "FMNMX_R"),
INST("0011100-01100---", Id::FMNMX_IMM, Type::Arithmetic, "FMNMX_IMM"),
INST("000001----------", Id::LOP32I, Type::Logic, "LOP32I"),
+ INST("0100110001001---", Id::SHL_C, Type::Shift, "SHL_C"),
+ INST("0101110001001---", Id::SHL_R, Type::Shift, "SHL_R"),
+ INST("0011100-01001---", Id::SHL_IMM, Type::Shift, "SHL_IMM"),
+ INST("0100110000101---", Id::SHR_C, Type::Shift, "SHR_C"),
+ INST("0101110000101---", Id::SHR_R, Type::Shift, "SHR_R"),
+ INST("0011100-00101---", Id::SHR_IMM, Type::Shift, "SHR_IMM"),
INST("0100110011100---", Id::I2I_C, Type::Conversion, "I2I_C"),
INST("0101110011100---", Id::I2I_R, Type::Conversion, "I2I_R"),
INST("01110001-1000---", Id::I2I_IMM, Type::Conversion, "I2I_IMM"),
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index 4b14bb47e..4a41e7798 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -115,7 +115,16 @@ private:
if (const auto opcode = OpCode::Decode(instr)) {
switch (opcode->GetId()) {
case OpCode::Id::EXIT: {
- return exit_method = ExitMethod::AlwaysEnd;
+ // The EXIT instruction can be predicated, which means that the shader can
+ // conditionally end on this instruction. We have to consider the case where the
+ // condition is not met and check the exit method of that other basic block.
+ using Tegra::Shader::Pred;
+ if (instr.pred.pred_index == static_cast<u64>(Pred::UnusedIndex)) {
+ return exit_method = ExitMethod::AlwaysEnd;
+ } else {
+ ExitMethod not_met = Scan(offset + 1, end, labels);
+ return exit_method = ParallelExit(ExitMethod::AlwaysEnd, not_met);
+ }
}
case OpCode::Id::BRA: {
u32 target = offset + instr.bra.GetBranchTarget();
@@ -645,9 +654,9 @@ private:
std::string GetPredicateComparison(Tegra::Shader::PredCondition condition) const {
using Tegra::Shader::PredCondition;
static const std::unordered_map<PredCondition, const char*> PredicateComparisonStrings = {
- {PredCondition::LessThan, "<"}, {PredCondition::Equal, "=="},
- {PredCondition::LessEqual, "<="}, {PredCondition::GreaterThan, ">"},
- {PredCondition::GreaterEqual, ">="},
+ {PredCondition::LessThan, "<"}, {PredCondition::Equal, "=="},
+ {PredCondition::LessEqual, "<="}, {PredCondition::GreaterThan, ">"},
+ {PredCondition::NotEqual, "!="}, {PredCondition::GreaterEqual, ">="},
};
auto comparison = PredicateComparisonStrings.find(condition);
@@ -884,6 +893,59 @@ private:
}
break;
}
+
+ case OpCode::Type::Shift: {
+ std::string op_a = regs.GetRegisterAsInteger(instr.gpr8, 0, false);
+ std::string op_b;
+
+ if (instr.is_b_imm) {
+ op_b += '(' + std::to_string(instr.alu.GetSignedImm20_20()) + ')';
+ } else {
+ if (instr.is_b_gpr) {
+ op_b += regs.GetRegisterAsInteger(instr.gpr20);
+ } else {
+ op_b += regs.GetUniform(instr.uniform, GLSLRegister::Type::Integer);
+ }
+ }
+
+ switch (opcode->GetId()) {
+ case OpCode::Id::SHL_C:
+ case OpCode::Id::SHL_R:
+ case OpCode::Id::SHL_IMM:
+ regs.SetRegisterToInteger(instr.gpr0, true, 0, op_a + " << " + op_b, 1, 1);
+ break;
+ default: {
+ NGLOG_CRITICAL(HW_GPU, "Unhandled shift instruction: {}", opcode->GetName());
+ UNREACHABLE();
+ }
+ }
+ break;
+ }
+
+ case OpCode::Type::ScaledAdd: {
+ std::string op_a = regs.GetRegisterAsInteger(instr.gpr8);
+
+ if (instr.iscadd.negate_a)
+ op_a = '-' + op_a;
+
+ std::string op_b = instr.iscadd.negate_b ? "-" : "";
+
+ if (instr.is_b_imm) {
+ op_b += '(' + std::to_string(instr.alu.GetSignedImm20_20()) + ')';
+ } else {
+ if (instr.is_b_gpr) {
+ op_b += regs.GetRegisterAsInteger(instr.gpr20);
+ } else {
+ op_b += regs.GetUniform(instr.uniform, GLSLRegister::Type::Integer);
+ }
+ }
+
+ std::string shift = std::to_string(instr.iscadd.shift_amount.Value());
+
+ regs.SetRegisterToInteger(instr.gpr0, true, 0,
+ "((" + op_a + " << " + shift + ") + " + op_b + ')', 1, 1);
+ break;
+ }
case OpCode::Type::Ffma: {
std::string op_a = regs.GetRegisterAsFloat(instr.gpr8);
std::string op_b = instr.ffma.negate_b ? "-" : "";
@@ -1230,9 +1292,6 @@ private:
default: {
switch (opcode->GetId()) {
case OpCode::Id::EXIT: {
- ASSERT_MSG(instr.pred.pred_index == static_cast<u64>(Pred::UnusedIndex),
- "Predicated exits not implemented");
-
// Final color output is currently hardcoded to GPR0-3 for fragment shaders
if (stage == Maxwell3D::Regs::ShaderStage::Fragment) {
shader.AddLine("color.r = " + regs.GetRegisterAsFloat(0) + ';');
@@ -1242,7 +1301,12 @@ private:
}
shader.AddLine("return true;");
- offset = PROGRAM_END - 1;
+ if (instr.pred.pred_index == static_cast<u64>(Pred::UnusedIndex)) {
+ // If this is an unconditional exit then just end processing here, otherwise we
+ // have to account for the possibility of the condition not being met, so
+ // continue processing the next instruction.
+ offset = PROGRAM_END - 1;
+ }
break;
}
case OpCode::Id::KIL: {
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 04:05:27 +0200