summaryrefslogtreecommitdiffstats
path: root/src
diff options
context:
space:
mode:
authorbunnei <bunneidev@gmail.com>2018-06-09 06:01:17 +0200
committerbunnei <bunneidev@gmail.com>2018-06-09 06:01:17 +0200
commit5440b9c634555c174a9eaf7fd6d308c4ab2cb3bb (patch)
treeb491f11a8e2ddb023c66b709c2f19c8b38de2c97 /src
parentMerge pull request #505 from janisozaur/ccache-travis (diff)
downloadyuzu-5440b9c634555c174a9eaf7fd6d308c4ab2cb3bb.tar
yuzu-5440b9c634555c174a9eaf7fd6d308c4ab2cb3bb.tar.gz
yuzu-5440b9c634555c174a9eaf7fd6d308c4ab2cb3bb.tar.bz2
yuzu-5440b9c634555c174a9eaf7fd6d308c4ab2cb3bb.tar.lz
yuzu-5440b9c634555c174a9eaf7fd6d308c4ab2cb3bb.tar.xz
yuzu-5440b9c634555c174a9eaf7fd6d308c4ab2cb3bb.tar.zst
yuzu-5440b9c634555c174a9eaf7fd6d308c4ab2cb3bb.zip
Diffstat (limited to '')
-rw-r--r--src/video_core/engines/shader_bytecode.h4
-rw-r--r--src/video_core/renderer_opengl/gl_shader_decompiler.cpp13
2 files changed, 17 insertions, 0 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index 32800392b..a9ea550dc 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -260,6 +260,10 @@ union Instruction {
} alu;
union {
+ BitField<48, 1, u64> is_signed;
+ } shift;
+
+ union {
BitField<39, 5, u64> shift_amount;
BitField<48, 1, u64> negate_b;
BitField<49, 1, u64> negate_a;
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index 94c6bc4b2..fde19cb6b 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -973,6 +973,19 @@ private:
}
switch (opcode->GetId()) {
+ case OpCode::Id::SHR_C:
+ case OpCode::Id::SHR_R:
+ case OpCode::Id::SHR_IMM: {
+ if (!instr.shift.is_signed) {
+ // Logical shift right
+ op_a = "uint(" + op_a + ')';
+ }
+
+ // Cast to int is superfluous for arithmetic shift, it's only for a logical shift
+ regs.SetRegisterToInteger(instr.gpr0, true, 0, "int(" + op_a + " >> " + op_b + ')',
+ 1, 1);
+ break;
+ }
case OpCode::Id::SHL_C:
case OpCode::Id::SHL_R:
case OpCode::Id::SHL_IMM: