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author | Fernando S <fsahmkow27@gmail.com> | 2022-12-08 12:41:39 +0100 |
---|---|---|
committer | GitHub <noreply@github.com> | 2022-12-08 12:41:39 +0100 |
commit | 41461514d6f3ba59dc027dbc4a88c0ffb570ea49 (patch) | |
tree | c3cffc17ce63e66f5fa2921e4804c396140a9791 /src/video_core/renderer_vulkan/fixed_pipeline_state.cpp | |
parent | Merge pull request #9365 from liamwhite/val (diff) | |
parent | video_core: Implement maxwell3d draw manager and split draw logic (diff) | |
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Diffstat (limited to '')
-rw-r--r-- | src/video_core/renderer_vulkan/fixed_pipeline_state.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/video_core/renderer_vulkan/fixed_pipeline_state.cpp b/src/video_core/renderer_vulkan/fixed_pipeline_state.cpp index 5864e772b..e62b36822 100644 --- a/src/video_core/renderer_vulkan/fixed_pipeline_state.cpp +++ b/src/video_core/renderer_vulkan/fixed_pipeline_state.cpp @@ -8,6 +8,7 @@ #include "common/cityhash.h" #include "common/common_types.h" #include "common/polyfill_ranges.h" +#include "video_core/engines/draw_manager.h" #include "video_core/renderer_vulkan/fixed_pipeline_state.h" #include "video_core/renderer_vulkan/vk_state_tracker.h" @@ -50,12 +51,13 @@ void RefreshXfbState(VideoCommon::TransformFeedbackState& state, const Maxwell& void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d, bool has_extended_dynamic_state, bool has_dynamic_vertex_input) { const Maxwell& regs = maxwell3d.regs; + const auto topology_ = maxwell3d.draw_manager->GetDrawState().topology; const std::array enabled_lut{ regs.polygon_offset_point_enable, regs.polygon_offset_line_enable, regs.polygon_offset_fill_enable, }; - const u32 topology_index = static_cast<u32>(regs.draw.topology.Value()); + const u32 topology_index = static_cast<u32>(topology_); raw1 = 0; extended_dynamic_state.Assign(has_extended_dynamic_state ? 1 : 0); @@ -78,7 +80,7 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d, Maxwell::Tessellation::OutputPrimitives::Triangles_CW); logic_op_enable.Assign(regs.logic_op.enable != 0 ? 1 : 0); logic_op.Assign(PackLogicOp(regs.logic_op.op)); - topology.Assign(regs.draw.topology); + topology.Assign(topology_); msaa_mode.Assign(regs.anti_alias_samples_mode); raw2 = 0; |