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authorSubv <subv2112@gmail.com>2015-04-11 20:53:35 +0200
committerSubv <subv2112@gmail.com>2015-05-07 01:11:46 +0200
commit0e5ca080a86a6e393eab1a11075561a62a2e01f9 (patch)
treecf37d6291c720f06311a5403acb37d5b6a82d18e /src/video_core/pica.h
parentMerge pull request #683 from bunnei/thread-priority (diff)
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Diffstat (limited to '')
-rw-r--r--src/video_core/pica.h67
1 files changed, 42 insertions, 25 deletions
diff --git a/src/video_core/pica.h b/src/video_core/pica.h
index fe20cd77d..8acad8676 100644
--- a/src/video_core/pica.h
+++ b/src/video_core/pica.h
@@ -489,14 +489,14 @@ struct Regs {
INSERT_PADDING_WORDS(0xe0);
- struct {
- enum class Format : u64 {
- BYTE = 0,
- UBYTE = 1,
- SHORT = 2,
- FLOAT = 3,
- };
+ enum class VertexAttributeFormat : u64 {
+ BYTE = 0,
+ UBYTE = 1,
+ SHORT = 2,
+ FLOAT = 3,
+ };
+ struct {
BitField<0, 29, u32> base_address;
u32 GetPhysicalBaseAddress() const {
@@ -505,29 +505,29 @@ struct Regs {
// Descriptor for internal vertex attributes
union {
- BitField< 0, 2, Format> format0; // size of one element
+ BitField< 0, 2, VertexAttributeFormat> format0; // size of one element
BitField< 2, 2, u64> size0; // number of elements minus 1
- BitField< 4, 2, Format> format1;
+ BitField< 4, 2, VertexAttributeFormat> format1;
BitField< 6, 2, u64> size1;
- BitField< 8, 2, Format> format2;
+ BitField< 8, 2, VertexAttributeFormat> format2;
BitField<10, 2, u64> size2;
- BitField<12, 2, Format> format3;
+ BitField<12, 2, VertexAttributeFormat> format3;
BitField<14, 2, u64> size3;
- BitField<16, 2, Format> format4;
+ BitField<16, 2, VertexAttributeFormat> format4;
BitField<18, 2, u64> size4;
- BitField<20, 2, Format> format5;
+ BitField<20, 2, VertexAttributeFormat> format5;
BitField<22, 2, u64> size5;
- BitField<24, 2, Format> format6;
+ BitField<24, 2, VertexAttributeFormat> format6;
BitField<26, 2, u64> size6;
- BitField<28, 2, Format> format7;
+ BitField<28, 2, VertexAttributeFormat> format7;
BitField<30, 2, u64> size7;
- BitField<32, 2, Format> format8;
+ BitField<32, 2, VertexAttributeFormat> format8;
BitField<34, 2, u64> size8;
- BitField<36, 2, Format> format9;
+ BitField<36, 2, VertexAttributeFormat> format9;
BitField<38, 2, u64> size9;
- BitField<40, 2, Format> format10;
+ BitField<40, 2, VertexAttributeFormat> format10;
BitField<42, 2, u64> size10;
- BitField<44, 2, Format> format11;
+ BitField<44, 2, VertexAttributeFormat> format11;
BitField<46, 2, u64> size11;
BitField<48, 12, u64> attribute_mask;
@@ -536,8 +536,8 @@ struct Regs {
BitField<60, 4, u64> num_extra_attributes;
};
- inline Format GetFormat(int n) const {
- Format formats[] = {
+ inline VertexAttributeFormat GetFormat(int n) const {
+ VertexAttributeFormat formats[] = {
format0, format1, format2, format3,
format4, format5, format6, format7,
format8, format9, format10, format11
@@ -555,14 +555,18 @@ struct Regs {
}
inline int GetElementSizeInBytes(int n) const {
- return (GetFormat(n) == Format::FLOAT) ? 4 :
- (GetFormat(n) == Format::SHORT) ? 2 : 1;
+ return (GetFormat(n) == VertexAttributeFormat::FLOAT) ? 4 :
+ (GetFormat(n) == VertexAttributeFormat::SHORT) ? 2 : 1;
}
inline int GetStride(int n) const {
return GetNumElements(n) * GetElementSizeInBytes(n);
}
+ inline bool IsDefaultAttribute(int id) const {
+ return (id >= 12) || (attribute_mask & (1 << id)) != 0;
+ }
+
inline int GetNumTotalAttributes() const {
return (int)num_extra_attributes+1;
}
@@ -625,7 +629,18 @@ struct Regs {
u32 trigger_draw;
u32 trigger_draw_indexed;
- INSERT_PADDING_WORDS(0x2e);
+ INSERT_PADDING_WORDS(0x2);
+
+ // These registers are used to setup the default "fall-back" vertex shader attributes
+ struct {
+ // Index of the current default attribute
+ u32 index;
+
+ // Writing to these registers sets the "current" default attribute.
+ u32 set_value[3];
+ } vs_default_attributes_setup;
+
+ INSERT_PADDING_WORDS(0x28);
enum class TriangleTopology : u32 {
List = 0,
@@ -669,7 +684,7 @@ struct Regs {
BitField<56, 4, u64> attribute14_register;
BitField<60, 4, u64> attribute15_register;
- int GetRegisterForAttribute(int attribute_index) {
+ int GetRegisterForAttribute(int attribute_index) const {
u64 fields[] = {
attribute0_register, attribute1_register, attribute2_register, attribute3_register,
attribute4_register, attribute5_register, attribute6_register, attribute7_register,
@@ -775,6 +790,7 @@ struct Regs {
ADD_FIELD(num_vertices);
ADD_FIELD(trigger_draw);
ADD_FIELD(trigger_draw_indexed);
+ ADD_FIELD(vs_default_attributes_setup);
ADD_FIELD(triangle_topology);
ADD_FIELD(vs_bool_uniforms);
ADD_FIELD(vs_int_uniforms);
@@ -849,6 +865,7 @@ ASSERT_REG_POSITION(index_array, 0x227);
ASSERT_REG_POSITION(num_vertices, 0x228);
ASSERT_REG_POSITION(trigger_draw, 0x22e);
ASSERT_REG_POSITION(trigger_draw_indexed, 0x22f);
+ASSERT_REG_POSITION(vs_default_attributes_setup, 0x232);
ASSERT_REG_POSITION(triangle_topology, 0x25e);
ASSERT_REG_POSITION(vs_bool_uniforms, 0x2b0);
ASSERT_REG_POSITION(vs_int_uniforms, 0x2b1);