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| author | bunnei <bunneidev@gmail.com> | 2018-06-06 04:01:29 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-06-06 04:01:29 +0200 |
| commit | 5fb99e6a166786eab5e1f8c656fe8431b3e11255 (patch) | |
| tree | f9a689d4c732095234417560247a32622df39be8 /src/video_core/engines | |
| parent | Merge pull request #523 from yuzu-emu/revert-507-3616 (diff) | |
| parent | GPU: Implemented the F2I_R shader instruction. (diff) | |
| download | yuzu-5fb99e6a166786eab5e1f8c656fe8431b3e11255.tar yuzu-5fb99e6a166786eab5e1f8c656fe8431b3e11255.tar.gz yuzu-5fb99e6a166786eab5e1f8c656fe8431b3e11255.tar.bz2 yuzu-5fb99e6a166786eab5e1f8c656fe8431b3e11255.tar.lz yuzu-5fb99e6a166786eab5e1f8c656fe8431b3e11255.tar.xz yuzu-5fb99e6a166786eab5e1f8c656fe8431b3e11255.tar.zst yuzu-5fb99e6a166786eab5e1f8c656fe8431b3e11255.zip | |
Diffstat (limited to '')
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 38757c038..4eb507325 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -173,6 +173,13 @@ enum class SubOp : u64 { Min = 0x8, }; +enum class FloatRoundingOp : u64 { + None = 0, + Floor = 1, + Ceil = 2, + Trunc = 3, +}; + union Instruction { Instruction& operator=(const Instruction& instr) { value = instr.value; @@ -290,11 +297,20 @@ union Instruction { union { BitField<10, 2, Register::Size> size; - BitField<13, 1, u64> is_signed; + BitField<12, 1, u64> is_output_signed; + BitField<13, 1, u64> is_input_signed; BitField<41, 2, u64> selector; BitField<45, 1, u64> negate_a; BitField<49, 1, u64> abs_a; BitField<50, 1, u64> saturate_a; + + union { + BitField<39, 2, FloatRoundingOp> rounding; + } f2i; + + union { + BitField<39, 4, u64> rounding; + } f2f; } conversion; union { @@ -560,9 +576,9 @@ private: INST("0100110010101---", Id::F2F_C, Type::Conversion, "F2F_C"), INST("0101110010101---", Id::F2F_R, Type::Conversion, "F2F_R"), INST("0011100-10101---", Id::F2F_IMM, Type::Conversion, "F2F_IMM"), - INST("0100110010110---", Id::F2I_C, Type::Arithmetic, "F2I_C"), - INST("0101110010110---", Id::F2I_R, Type::Arithmetic, "F2I_R"), - INST("0011100-10110---", Id::F2I_IMM, Type::Arithmetic, "F2I_IMM"), + INST("0100110010110---", Id::F2I_C, Type::Conversion, "F2I_C"), + INST("0101110010110---", Id::F2I_R, Type::Conversion, "F2I_R"), + INST("0011100-10110---", Id::F2I_IMM, Type::Conversion, "F2I_IMM"), INST("0100110010011---", Id::MOV_C, Type::Arithmetic, "MOV_C"), INST("0101110010011---", Id::MOV_R, Type::Arithmetic, "MOV_R"), INST("0011100-10011---", Id::MOV_IMM, Type::Arithmetic, "MOV_IMM"), |