summaryrefslogtreecommitdiffstats
path: root/src/video_core/engines/maxwell_3d.cpp
diff options
context:
space:
mode:
authorSubv <subv2112@gmail.com>2018-06-06 19:58:16 +0200
committerSubv <subv2112@gmail.com>2018-06-06 19:58:16 +0200
commitdbfc39d21492dd1346b0e0d7ab5a2dbd989432bd (patch)
treefa95ce57c5f16a01b766efe2b49ed90888800e3d /src/video_core/engines/maxwell_3d.cpp
parentnvdrv/devices/nvidia_ctrl_gpu : add IoctlCommands with their params (#524) (diff)
downloadyuzu-dbfc39d21492dd1346b0e0d7ab5a2dbd989432bd.tar
yuzu-dbfc39d21492dd1346b0e0d7ab5a2dbd989432bd.tar.gz
yuzu-dbfc39d21492dd1346b0e0d7ab5a2dbd989432bd.tar.bz2
yuzu-dbfc39d21492dd1346b0e0d7ab5a2dbd989432bd.tar.lz
yuzu-dbfc39d21492dd1346b0e0d7ab5a2dbd989432bd.tar.xz
yuzu-dbfc39d21492dd1346b0e0d7ab5a2dbd989432bd.tar.zst
yuzu-dbfc39d21492dd1346b0e0d7ab5a2dbd989432bd.zip
Diffstat (limited to '')
-rw-r--r--src/video_core/engines/maxwell_3d.cpp34
1 files changed, 34 insertions, 0 deletions
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index ef12d9300..86e9dc998 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -354,6 +354,40 @@ std::vector<Texture::FullTextureInfo> Maxwell3D::GetStageTextures(Regs::ShaderSt
return textures;
}
+Texture::FullTextureInfo Maxwell3D::GetStageTexture(Regs::ShaderStage stage, size_t offset) const {
+ auto& shader = state.shader_stages[static_cast<size_t>(stage)];
+ auto& tex_info_buffer = shader.const_buffers[regs.tex_cb_index];
+ ASSERT(tex_info_buffer.enabled && tex_info_buffer.address != 0);
+
+ GPUVAddr tex_info_address = tex_info_buffer.address + offset * sizeof(Texture::TextureHandle);
+
+ ASSERT(tex_info_address < tex_info_buffer.address + tex_info_buffer.size);
+
+ boost::optional<VAddr> tex_address_cpu = memory_manager.GpuToCpuAddress(tex_info_address);
+ Texture::TextureHandle tex_handle{Memory::Read32(*tex_address_cpu)};
+
+ Texture::FullTextureInfo tex_info{};
+ tex_info.index = static_cast<u32>(offset);
+
+ // Load the TIC data.
+ if (tex_handle.tic_id != 0) {
+ tex_info.enabled = true;
+
+ auto tic_entry = GetTICEntry(tex_handle.tic_id);
+ // TODO(Subv): Workaround for BitField's move constructor being deleted.
+ std::memcpy(&tex_info.tic, &tic_entry, sizeof(tic_entry));
+ }
+
+ // Load the TSC data
+ if (tex_handle.tsc_id != 0) {
+ auto tsc_entry = GetTSCEntry(tex_handle.tsc_id);
+ // TODO(Subv): Workaround for BitField's move constructor being deleted.
+ std::memcpy(&tex_info.tsc, &tsc_entry, sizeof(tsc_entry));
+ }
+
+ return tex_info;
+}
+
u32 Maxwell3D::GetRegisterValue(u32 method) const {
ASSERT_MSG(method < Regs::NUM_REGS, "Invalid Maxwell3D register");
return regs.reg_array[method];