diff options
author | Fernando S <fsahmkow27@gmail.com> | 2021-11-14 23:03:56 +0100 |
---|---|---|
committer | GitHub <noreply@github.com> | 2021-11-14 23:03:56 +0100 |
commit | 720970c4c1d71c67fa8af1e86c78d9141148729b (patch) | |
tree | d33d5f3fe85da3811932b590ebe459eb6e08a5ac /src/video_core/command_classes/nvdec_common.h | |
parent | Merge pull request #7260 from vonchenplus/spirv_support_legacy_attribute_v2 (diff) | |
parent | codes: Rename ComposeFrameHeader to ComposeFrame (diff) | |
download | yuzu-720970c4c1d71c67fa8af1e86c78d9141148729b.tar yuzu-720970c4c1d71c67fa8af1e86c78d9141148729b.tar.gz yuzu-720970c4c1d71c67fa8af1e86c78d9141148729b.tar.bz2 yuzu-720970c4c1d71c67fa8af1e86c78d9141148729b.tar.lz yuzu-720970c4c1d71c67fa8af1e86c78d9141148729b.tar.xz yuzu-720970c4c1d71c67fa8af1e86c78d9141148729b.tar.zst yuzu-720970c4c1d71c67fa8af1e86c78d9141148729b.zip |
Diffstat (limited to '')
-rw-r--r-- | src/video_core/command_classes/nvdec_common.h | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/video_core/command_classes/nvdec_common.h b/src/video_core/command_classes/nvdec_common.h index 6a24e00a0..8a35c44a1 100644 --- a/src/video_core/command_classes/nvdec_common.h +++ b/src/video_core/command_classes/nvdec_common.h @@ -13,9 +13,9 @@ namespace Tegra::NvdecCommon { enum class VideoCodec : u64 { None = 0x0, H264 = 0x3, - Vp8 = 0x5, + VP8 = 0x5, H265 = 0x7, - Vp9 = 0x9, + VP9 = 0x9, }; // NVDEC should use a 32-bit address space, but is mapped to 64-bit, @@ -50,7 +50,10 @@ struct NvdecRegisters { u64 h264_last_surface_chroma_offset; ///< 0x0858 std::array<u64, 17> surface_luma_offset; ///< 0x0860 std::array<u64, 17> surface_chroma_offset; ///< 0x08E8 - INSERT_PADDING_WORDS_NOINIT(132); ///< 0x0970 + INSERT_PADDING_WORDS_NOINIT(68); ///< 0x0970 + u64 vp8_prob_data_offset; ///< 0x0A80 + u64 vp8_header_partition_buf_offset; ///< 0x0A88 + INSERT_PADDING_WORDS_NOINIT(60); ///< 0x0A90 u64 vp9_entropy_probs_offset; ///< 0x0B80 u64 vp9_backward_updates_offset; ///< 0x0B88 u64 vp9_last_frame_segmap_offset; ///< 0x0B90 @@ -81,6 +84,8 @@ ASSERT_REG_POSITION(h264_last_surface_luma_offset, 0x10A); ASSERT_REG_POSITION(h264_last_surface_chroma_offset, 0x10B); ASSERT_REG_POSITION(surface_luma_offset, 0x10C); ASSERT_REG_POSITION(surface_chroma_offset, 0x11D); +ASSERT_REG_POSITION(vp8_prob_data_offset, 0x150); +ASSERT_REG_POSITION(vp8_header_partition_buf_offset, 0x151); ASSERT_REG_POSITION(vp9_entropy_probs_offset, 0x170); ASSERT_REG_POSITION(vp9_backward_updates_offset, 0x171); ASSERT_REG_POSITION(vp9_last_frame_segmap_offset, 0x172); |