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authorameerj <52414509+ameerj@users.noreply.github.com>2021-03-29 02:16:26 +0200
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-23 03:51:25 +0200
commitcd9f75e2239666a932861f6d54138febf8736a8c (patch)
tree06275f7cbf8634f2d0c920a1831fbaa8837b7c37 /src/shader_recompiler/frontend
parentshader: Implement LDS, STS, LDL, and STS and use SPIR-V 1.4 when available (diff)
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Diffstat (limited to '')
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/integer_scaled_add.cpp15
1 files changed, 8 insertions, 7 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_scaled_add.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_scaled_add.cpp
index 7aef37f54..93cc2c0b1 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_scaled_add.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_scaled_add.cpp
@@ -30,23 +30,24 @@ void ISCADD(TranslatorVisitor& v, u64 insn, IR::U32 op_b) {
if (iscadd.neg_b != 0) {
op_b = v.ir.INeg(op_b);
}
+ } else {
+ // When PO is present, add one
+ op_b = v.ir.IAdd(op_b, v.ir.Imm32(1));
}
// With the operands already processed, scale A
const IR::U32 scale{v.ir.Imm32(static_cast<u32>(iscadd.scale))};
const IR::U32 scaled_a{v.ir.ShiftLeftLogical(op_a, scale)};
- IR::U32 result{v.ir.IAdd(scaled_a, op_b)};
- if (po) {
- // .PO adds one to the final result
- result = v.ir.IAdd(result, v.ir.Imm32(1));
- }
+ const IR::U32 result{v.ir.IAdd(scaled_a, op_b)};
v.X(iscadd.dest_reg, result);
if (iscadd.cc != 0) {
v.SetZFlag(v.ir.GetZeroFromOp(result));
v.SetSFlag(v.ir.GetSignFromOp(result));
- v.SetCFlag(v.ir.GetCarryFromOp(result));
- v.SetOFlag(v.ir.GetOverflowFromOp(result));
+ const IR::U1 carry{v.ir.GetCarryFromOp(result)};
+ const IR::U1 overflow{v.ir.GetOverflowFromOp(result)};
+ v.SetCFlag(po ? v.ir.LogicalOr(carry, v.ir.GetCarryFromOp(op_b)) : carry);
+ v.SetOFlag(po ? v.ir.LogicalOr(overflow, v.ir.GetOverflowFromOp(op_b)) : overflow);
}
}