1 files changed, 14 insertions, 2 deletions

diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/predicate_set_register.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/predicate_set_register.cpp
index 6c15963fa..b02789874 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/predicate_set_register.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/predicate_set_register.cpp
@@ -21,6 +21,7 @@ void TranslatorVisitor::PSET(u64 insn) {
         BitField<42, 1, u64> neg_pred_c;
         BitField<44, 1, u64> bf;
         BitField<45, 2, BooleanOp> bop_2;
+        BitField<47, 1, u64> cc;
     } const pset{insn};
 
     const IR::U1 pred_a{ir.GetPred(pset.pred_a, pset.neg_pred_a != 0)};
@@ -31,11 +32,22 @@ void TranslatorVisitor::PSET(u64 insn) {
     const IR::U1 res_2{PredicateCombine(ir, res_1, pred_c, pset.bop_2)};
 
     const IR::U32 true_result{pset.bf != 0 ? ir.Imm32(0x3f800000) : ir.Imm32(-1)};
-    const IR::U32 false_result{ir.Imm32(0)};
+    const IR::U32 zero{ir.Imm32(0)};
 
-    const IR::U32 result{ir.Select(res_2, true_result, false_result)};
+    const IR::U32 result{ir.Select(res_2, true_result, zero)};
 
     X(pset.dest_reg, result);
+    if (pset.cc != 0) {
+        const IR::U1 is_zero{ir.IEqual(result, zero)};
+        SetZFlag(is_zero);
+        if (pset.bf != 0) {
+            ResetSFlag();
+        } else {
+            SetSFlag(ir.LogicalNot(is_zero));
+        }
+        ResetOFlag();
+        ResetCFlag();
+    }
 }
 
 } // namespace Shader::Maxwell