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| author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2021-05-18 07:04:22 +0200 |
|---|---|---|
| committer | ameerj <52414509+ameerj@users.noreply.github.com> | 2021-07-23 03:51:32 +0200 |
| commit | 9bb3e008c9f4bbdd35c095b506c3a3312d17e383 (patch) | |
| tree | 320cc594970b6ef658d8bed88ceabded0f84caea /src/shader_recompiler/backend/glasm/reg_alloc.cpp | |
| parent | glasm: Implement InstanceId and VertexId (diff) | |
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Diffstat (limited to '')
| -rw-r--r-- | src/shader_recompiler/backend/glasm/reg_alloc.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/shader_recompiler/backend/glasm/reg_alloc.cpp b/src/shader_recompiler/backend/glasm/reg_alloc.cpp index 707b22247..1a88331b4 100644 --- a/src/shader_recompiler/backend/glasm/reg_alloc.cpp +++ b/src/shader_recompiler/backend/glasm/reg_alloc.cpp @@ -139,6 +139,7 @@ void RegAlloc::Free(Id id) { /*static*/ bool RegAlloc::IsAliased(const IR::Inst& inst) { switch (inst.GetOpcode()) { case IR::Opcode::Identity: + case IR::Opcode::ConditionRef: case IR::Opcode::BitCastU16F16: case IR::Opcode::BitCastU32F32: case IR::Opcode::BitCastU64F64: |