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authorLioncash <mathew1800@gmail.com>2015-04-06 19:01:19 +0200
committerLioncash <mathew1800@gmail.com>2015-04-06 19:01:19 +0200
commit8004d35ea163b621ea3f3d4333f2c58ec926d7c9 (patch)
tree5e81e78b4789fe9d6c1c6c54836d1e338ec7714a /src/core
parentarm_interface: Support retrieval/storage to CP15 registers (diff)
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Diffstat (limited to '')
-rw-r--r--src/core/arm/interpreter/arminit.cpp8
-rw-r--r--src/core/core.cpp5
2 files changed, 5 insertions, 8 deletions
diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp
index 7254a16f3..1d732fe84 100644
--- a/src/core/arm/interpreter/arminit.cpp
+++ b/src/core/arm/interpreter/arminit.cpp
@@ -139,16 +139,8 @@ void ARMul_Reset(ARMul_State* state)
state->Bank = SVCBANK;
FLUSHPIPE;
- // Reset CP15
ResetMPCoreCP15Registers(state);
- // This is separate from the CP15 register reset function, as
- // this isn't an ARM-defined reset value; it's set by the 3DS.
- //
- // TODO: Whenever TLS is implemented, this should contain
- // the address of the 0x200-byte TLS
- state->CP15[CP15_THREAD_URO] = Memory::KERNEL_MEMORY_VADDR;
-
state->EndCondition = 0;
state->ErrorCode = 0;
diff --git a/src/core/core.cpp b/src/core/core.cpp
index 15787bc17..81e642318 100644
--- a/src/core/core.cpp
+++ b/src/core/core.cpp
@@ -7,6 +7,7 @@
#include "core/core.h"
#include "core/core_timing.h"
+#include "core/mem_map.h"
#include "core/settings.h"
#include "core/arm/arm_interface.h"
#include "core/arm/disassembler/arm_disasm.h"
@@ -59,6 +60,10 @@ int Init() {
g_sys_core = new ARM_DynCom(USER32MODE);
g_app_core = new ARM_DynCom(USER32MODE);
+ // TODO: Whenever TLS is implemented, this should contain
+ // the address of the 0x200-byte TLS
+ g_app_core->SetCP15Register(CP15_THREAD_URO, Memory::KERNEL_MEMORY_VADDR);
+
LOG_DEBUG(Core, "Initialized OK");
return 0;
}