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| author | Emmanuel Gil Peyrot <linkmauve@linkmauve.fr> | 2016-09-18 02:38:01 +0200 |
|---|---|---|
| committer | Emmanuel Gil Peyrot <linkmauve@linkmauve.fr> | 2016-09-18 02:38:01 +0200 |
| commit | dc8479928c5aee4c6ad6fe4f59006fb604cee701 (patch) | |
| tree | 569a7f13128450bbab973236615587ff00bced5f /src/core/arm | |
| parent | Travis: Import Dolphin’s clang-format hook. (diff) | |
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Diffstat (limited to '')
22 files changed, 5726 insertions, 6274 deletions
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h index 480c90e66..919da6737 100644 --- a/src/core/arm/arm_interface.h +++ b/src/core/arm/arm_interface.h @@ -9,7 +9,7 @@ #include "core/arm/skyeye_common/vfp/asm_vfp.h" namespace Core { - struct ThreadContext; +struct ThreadContext; } /// Generic ARM11 CPU interface @@ -141,10 +141,10 @@ public: return num_instructions; } - s64 down_count = 0; ///< A decreasing counter of remaining cycles before the next event, decreased by the cpu run loop + s64 down_count = 0; ///< A decreasing counter of remaining cycles before the next event, + /// decreased by the cpu run loop protected: - /** * Executes the given number of instructions * @param num_instructions Number of instructions to executes @@ -152,6 +152,5 @@ protected: virtual void ExecuteInstructions(int num_instructions) = 0; private: - u64 num_instructions = 0; ///< Number of instructions executed }; diff --git a/src/core/arm/disassembler/arm_disasm.cpp b/src/core/arm/disassembler/arm_disasm.cpp index 5ad1f1c29..b3b9971e8 100644 --- a/src/core/arm/disassembler/arm_disasm.cpp +++ b/src/core/arm/disassembler/arm_disasm.cpp @@ -9,401 +9,225 @@ #include "core/arm/disassembler/arm_disasm.h" #include "core/arm/skyeye_common/armsupp.h" -static const char *cond_names[] = { - "eq", - "ne", - "cs", - "cc", - "mi", - "pl", - "vs", - "vc", - "hi", - "ls", - "ge", - "lt", - "gt", - "le", - "", - "RESERVED" -}; - -static const char *opcode_names[] = { - "invalid", - "undefined", - "adc", - "add", - "and", - "b", - "bl", - "bic", - "bkpt", - "blx", - "bx", - "cdp", - "clrex", - "clz", - "cmn", - "cmp", - "eor", - "ldc", - "ldm", - "ldr", - "ldrb", - "ldrbt", - "ldrex", - "ldrexb", - "ldrexd", - "ldrexh", - "ldrh", - "ldrsb", - "ldrsh", - "ldrt", - "mcr", - "mla", - "mov", - "mrc", - "mrs", - "msr", - "mul", - "mvn", - "nop", - "orr", - "pkh", - "pld", - "qadd16", - "qadd8", - "qasx", - "qsax", - "qsub16", - "qsub8", - "rev", - "rev16", - "revsh", - "rsb", - "rsc", - "sadd16", - "sadd8", - "sasx", - "sbc", - "sel", - "sev", - "shadd16", - "shadd8", - "shasx", - "shsax", - "shsub16", - "shsub8", - "smlad", - "smlal", - "smlald", - "smlsd", - "smlsld", - "smmla", - "smmls", - "smmul", - "smuad", - "smull", - "smusd", - "ssat", - "ssat16", - "ssax", - "ssub16", - "ssub8", - "stc", - "stm", - "str", - "strb", - "strbt", - "strex", - "strexb", - "strexd", - "strexh", - "strh", - "strt", - "sub", - "swi", - "swp", - "swpb", - "sxtab", - "sxtab16", - "sxtah", - "sxtb", - "sxtb16", - "sxth", - "teq", - "tst", - "uadd16", - "uadd8", - "uasx", - "uhadd16", - "uhadd8", - "uhasx", - "uhsax", - "uhsub16", - "uhsub8", - "umlal", - "umull", - "uqadd16", - "uqadd8", - "uqasx", - "uqsax", - "uqsub16", - "uqsub8", - "usad8", - "usada8", - "usat", - "usat16", - "usax", - "usub16", - "usub8", - "uxtab", - "uxtab16", - "uxtah", - "uxtb", - "uxtb16", - "uxth", - "wfe", - "wfi", +static const char* cond_names[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", + "hi", "ls", "ge", "lt", "gt", "le", "", "RESERVED"}; + +static const char* opcode_names[] = { + "invalid", "undefined", "adc", "add", "and", "b", "bl", "bic", + "bkpt", "blx", "bx", "cdp", "clrex", "clz", "cmn", "cmp", + "eor", "ldc", "ldm", "ldr", "ldrb", "ldrbt", "ldrex", "ldrexb", + "ldrexd", "ldrexh", "ldrh", "ldrsb", "ldrsh", "ldrt", "mcr", "mla", + "mov", "mrc", "mrs", "msr", "mul", "mvn", "nop", "orr", + "pkh", "pld", "qadd16", "qadd8", "qasx", "qsax", "qsub16", "qsub8", + "rev", "rev16", "revsh", "rsb", "rsc", "sadd16", "sadd8", "sasx", + "sbc", "sel", "sev", "shadd16", "shadd8", "shasx", "shsax", "shsub16", + "shsub8", "smlad", "smlal", "smlald", "smlsd", "smlsld", "smmla", "smmls", + "smmul", "smuad", "smull", "smusd", "ssat", "ssat16", "ssax", "ssub16", + "ssub8", "stc", "stm", "str", "strb", "strbt", "strex", "strexb", + "strexd", "strexh", "strh", "strt", "sub", "swi", "swp", "swpb", + "sxtab", "sxtab16", "sxtah", "sxtb", "sxtb16", "sxth", "teq", "tst", + "uadd16", "uadd8", "uasx", "uhadd16", "uhadd8", "uhasx", "uhsax", "uhsub16", + "uhsub8", "umlal", "umull", "uqadd16", "uqadd8", "uqasx", "uqsax", "uqsub16", + "uqsub8", "usad8", "usada8", "usat", "usat16", "usax", "usub16", "usub8", + "uxtab", "uxtab16", "uxtah", "uxtb", "uxtb16", "uxth", "wfe", "wfi", "yield", - "undefined", - "adc", - "add", - "and", - "asr", - "b", - "bic", - "bkpt", - "bl", - "blx", - "bx", - "cmn", - "cmp", - "eor", - "ldmia", - "ldr", - "ldrb", - "ldrh", - "ldrsb", - "ldrsh", - "lsl", - "lsr", - "mov", - "mul", - "mvn", - "neg", - "orr", - "pop", - "push", - "ror", - "sbc", - "stmia", - "str", - "strb", - "strh", - "sub", - "swi", - "tst", - - nullptr -}; + "undefined", "adc", "add", "and", "asr", "b", "bic", "bkpt", + "bl", "blx", "bx", "cmn", "cmp", "eor", "ldmia", "ldr", + "ldrb", "ldrh", "ldrsb", "ldrsh", "lsl", "lsr", "mov", "mul", + "mvn", "neg", "orr", "pop", "push", "ror", "sbc", "stmia", + "str", "strb", "strh", "sub", "swi", "tst", + + nullptr}; // Indexed by the shift type (bits 6-5) -static const char *shift_names[] = { - "LSL", - "LSR", - "ASR", - "ROR" -}; +static const char* shift_names[] = {"LSL", "LSR", "ASR", "ROR"}; static const char* cond_to_str(u32 cond) { return cond_names[cond]; } -std::string ARM_Disasm::Disassemble(u32 addr, u32 insn) -{ +std::string ARM_Disasm::Disassemble(u32 addr, u32 insn) { Opcode opcode = Decode(insn); switch (opcode) { - case OP_INVALID: - return "Invalid"; - case OP_UNDEFINED: - return "Undefined"; - case OP_ADC: - case OP_ADD: - case OP_AND: - case OP_BIC: - case OP_CMN: - case OP_CMP: - case OP_EOR: - case OP_MOV: - case OP_MVN: - case OP_ORR: - case OP_RSB: - case OP_RSC: - case OP_SBC: - case OP_SUB: - case OP_TEQ: - case OP_TST: - return DisassembleALU(opcode, insn); - case OP_B: - case OP_BL: - return DisassembleBranch(addr, opcode, insn); - case OP_BKPT: - return DisassembleBKPT(insn); - case OP_BLX: - // not supported yet - break; - case OP_BX: - return DisassembleBX(insn); - case OP_CDP: - return "cdp"; - case OP_CLREX: - return "clrex"; - case OP_CLZ: - return DisassembleCLZ(insn); - case OP_LDC: - return "ldc"; - case OP_LDM: - case OP_STM: - return DisassembleMemblock(opcode, insn); - case OP_LDR: - case OP_LDRB: - case OP_LDRBT: - case OP_LDRT: - case OP_STR: - case OP_STRB: - case OP_STRBT: - case OP_STRT: - return DisassembleMem(insn); - case OP_LDREX: - case OP_LDREXB: - case OP_LDREXD: - case OP_LDREXH: - case OP_STREX: - case OP_STREXB: - case OP_STREXD: - case OP_STREXH: - return DisassembleREX(opcode, insn); - case OP_LDRH: - case OP_LDRSB: - case OP_LDRSH: - case OP_STRH: - return DisassembleMemHalf(insn); - case OP_MCR: - case OP_MRC: - return DisassembleMCR(opcode, insn); - case OP_MLA: - return DisassembleMLA(opcode, insn); - case OP_MRS: - return DisassembleMRS(insn); - case OP_MSR: - return DisassembleMSR(insn); - case OP_MUL: - return DisassembleMUL(opcode, insn); - case OP_NOP: - case OP_SEV: - case OP_WFE: - case OP_WFI: - case OP_YIELD: - return DisassembleNoOperands(opcode, insn); - case OP_PKH: - return DisassemblePKH(insn); - case OP_PLD: - return DisassemblePLD(insn); - case OP_QADD16: - case OP_QADD8: - case OP_QASX: - case OP_QSAX: - case OP_QSUB16: - case OP_QSUB8: - case OP_SADD16: - case OP_SADD8: - case OP_SASX: - case OP_SHADD16: - case OP_SHADD8: - case OP_SHASX: - case OP_SHSAX: - case OP_SHSUB16: - case OP_SHSUB8: - case OP_SSAX: - case OP_SSUB16: - case OP_SSUB8: - case OP_UADD16: - case OP_UADD8: - case OP_UASX: - case OP_UHADD16: - case OP_UHADD8: - case OP_UHASX: - case OP_UHSAX: - case OP_UHSUB16: - case OP_UHSUB8: - case OP_UQADD16: - case OP_UQADD8: - case OP_UQASX: - case OP_UQSAX: - case OP_UQSUB16: - case OP_UQSUB8: - case OP_USAX: - case OP_USUB16: - case OP_USUB8: - return DisassembleParallelAddSub(opcode, insn); - case OP_REV: - case OP_REV16: - case OP_REVSH: - return DisassembleREV(opcode, insn); - case OP_SEL: - return DisassembleSEL(insn); - case OP_SMLAD: - case OP_SMLALD: - case OP_SMLSD: - case OP_SMLSLD: - case OP_SMMLA: - case OP_SMMLS: - case OP_SMMUL: - case OP_SMUAD: - case OP_SMUSD: - case OP_USAD8: - case OP_USADA8: - return DisassembleMediaMulDiv(opcode, insn); - case OP_SSAT: - case OP_SSAT16: - case OP_USAT: - case OP_USAT16: - return DisassembleSAT(opcode, insn); - case OP_STC: - return "stc"; - case OP_SWI: - return DisassembleSWI(insn); - case OP_SWP: - case OP_SWPB: - return DisassembleSWP(opcode, insn); - case OP_SXTAB: - case OP_SXTAB16: - case OP_SXTAH: - case OP_SXTB: - case OP_SXTB16: - case OP_SXTH: - case OP_UXTAB: - case OP_UXTAB16: - case OP_UXTAH: - case OP_UXTB: - case OP_UXTB16: - case OP_UXTH: - return DisassembleXT(opcode, insn); - case OP_UMLAL: - case OP_UMULL: - case OP_SMLAL: - case OP_SMULL: - return DisassembleUMLAL(opcode, insn); - default: - return "Error"; + case OP_INVALID: + return "Invalid"; + case OP_UNDEFINED: + return "Undefined"; + case OP_ADC: + case OP_ADD: + case OP_AND: + case OP_BIC: + case OP_CMN: + case OP_CMP: + case OP_EOR: + case OP_MOV: + case OP_MVN: + case OP_ORR: + case OP_RSB: + case OP_RSC: + case OP_SBC: + case OP_SUB: + case OP_TEQ: + case OP_TST: + return DisassembleALU(opcode, insn); + case OP_B: + case OP_BL: + return DisassembleBranch(addr, opcode, insn); + case OP_BKPT: + return DisassembleBKPT(insn); + case OP_BLX: + // not supported yet + break; + case OP_BX: + return DisassembleBX(insn); + case OP_CDP: + return "cdp"; + case OP_CLREX: + return "clrex"; + case OP_CLZ: + return DisassembleCLZ(insn); + case OP_LDC: + return "ldc"; + case OP_LDM: + case OP_STM: + return DisassembleMemblock(opcode, insn); + case OP_LDR: + case OP_LDRB: + case OP_LDRBT: + case OP_LDRT: + case OP_STR: + case OP_STRB: + case OP_STRBT: + case OP_STRT: + return DisassembleMem(insn); + case OP_LDREX: + case OP_LDREXB: + case OP_LDREXD: + case OP_LDREXH: + case OP_STREX: + case OP_STREXB: + case OP_STREXD: + case OP_STREXH: + return DisassembleREX(opcode, insn); + case OP_LDRH: + case OP_LDRSB: + case OP_LDRSH: + case OP_STRH: + return DisassembleMemHalf(insn); + case OP_MCR: + case OP_MRC: + return DisassembleMCR(opcode, insn); + case OP_MLA: + return DisassembleMLA(opcode, insn); + case OP_MRS: + return DisassembleMRS(insn); + case OP_MSR: + return DisassembleMSR(insn); + case OP_MUL: + return DisassembleMUL(opcode, insn); + case OP_NOP: + case OP_SEV: + case OP_WFE: + case OP_WFI: + case OP_YIELD: + return DisassembleNoOperands(opcode, insn); + case OP_PKH: + return DisassemblePKH(insn); + case OP_PLD: + return DisassemblePLD(insn); + case OP_QADD16: + case OP_QADD8: + case OP_QASX: + case OP_QSAX: + case OP_QSUB16: + case OP_QSUB8: + case OP_SADD16: + case OP_SADD8: + case OP_SASX: + case OP_SHADD16: + case OP_SHADD8: + case OP_SHASX: + case OP_SHSAX: + case OP_SHSUB16: + case OP_SHSUB8: + case OP_SSAX: + case OP_SSUB16: + case OP_SSUB8: + case OP_UADD16: + case OP_UADD8: + case OP_UASX: + case OP_UHADD16: + case OP_UHADD8: + case OP_UHASX: + case OP_UHSAX: + case OP_UHSUB16: + case OP_UHSUB8: + case OP_UQADD16: + case OP_UQADD8: + case OP_UQASX: + case OP_UQSAX: + case OP_UQSUB16: + case OP_UQSUB8: + case OP_USAX: + case OP_USUB16: + case OP_USUB8: + return DisassembleParallelAddSub(opcode, insn); + case OP_REV: + case OP_REV16: + case OP_REVSH: + return DisassembleREV(opcode, insn); + case OP_SEL: + return DisassembleSEL(insn); + case OP_SMLAD: + case OP_SMLALD: + case OP_SMLSD: + case OP_SMLSLD: + case OP_SMMLA: + case OP_SMMLS: + case OP_SMMUL: + case OP_SMUAD: + case OP_SMUSD: + case OP_USAD8: + case OP_USADA8: + return DisassembleMediaMulDiv(opcode, insn); + case OP_SSAT: + case OP_SSAT16: + case OP_USAT: + case OP_USAT16: + return DisassembleSAT(opcode, insn); + case OP_STC: + return "stc"; + case OP_SWI: + return DisassembleSWI(insn); + case OP_SWP: + case OP_SWPB: + return DisassembleSWP(opcode, insn); + case OP_SXTAB: + case OP_SXTAB16: + case OP_SXTAH: + case OP_SXTB: + case OP_SXTB16: + case OP_SXTH: + case OP_UXTAB: + case OP_UXTAB16: + case OP_UXTAH: + case OP_UXTB: + case OP_UXTB16: + case OP_UXTH: + return DisassembleXT(opcode, insn); + case OP_UMLAL: + case OP_UMULL: + case OP_SMLAL: + case OP_SMULL: + return DisassembleUMLAL(opcode, insn); + default: + return "Error"; } return nullptr; } -std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn) -{ +std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn) { static const u8 kNoOperand1 = 1; static const u8 kNoDest = 2; static const u8 kNoSbit = 4; @@ -421,18 +245,18 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn) const char* opname = opcode_names[opcode]; switch (opcode) { - case OP_CMN: - case OP_CMP: - case OP_TEQ: - case OP_TST: - flags = kNoDest | kNoSbit; - break; - case OP_MOV: - case OP_MVN: - flags = kNoOperand1; - break; - default: - break; + case OP_CMN: + case OP_CMP: + case OP_TEQ: + case OP_TST: + flags = kNoDest | kNoSbit; + break; + case OP_MOV: + case OP_MVN: + flags = kNoOperand1; + break; + default: + break; } // The "mov" instruction ignores the first operand (rn). @@ -448,13 +272,13 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn) rd_str = Common::StringFromFormat("r%d, ", rd); } - const char *sbit_str = ""; + const char* sbit_str = ""; if (bit_s && !(flags & kNoSbit)) sbit_str = "s"; if (is_immed) { - return Common::StringFromFormat("%s%s%s\t%s%s#%u ; 0x%x", - opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), immed, immed); + return Common::StringFromFormat("%s%s%s\t%s%s#%u ; 0x%x", opname, cond_to_str(cond), + sbit_str, rd_str.c_str(), rn_str.c_str(), immed, immed); } u8 shift_is_reg = (insn >> 4) & 1; @@ -468,30 +292,28 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn) rotated_val = (rotated_val >> rotate2) | (rotated_val << (32 - rotate2)); if (!shift_is_reg && shift_type == 0 && shift_amount == 0) { - return Common::StringFromFormat("%s%s%s\t%s%sr%d", - opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm); + return Common::StringFromFormat("%s%s%s\t%s%sr%d", opname, cond_to_str(cond), sbit_str, + rd_str.c_str(), rn_str.c_str(), rm); } - const char *shift_name = shift_names[shift_type]; + const char* shift_name = shift_names[shift_type]; if (shift_is_reg) { - return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s r%d", - opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm, - shift_name, rs); + return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s r%d", opname, cond_to_str(cond), + sbit_str, rd_str.c_str(), rn_str.c_str(), rm, shift_name, + rs); } if (shift_amount == 0) { if (shift_type == 3) { - return Common::StringFromFormat("%s%s%s\t%s%sr%d, RRX", - opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm); + return Common::StringFromFormat("%s%s%s\t%s%sr%d, RRX", opname, cond_to_str(cond), + sbit_str, rd_str.c_str(), rn_str.c_str(), rm); } shift_amount = 32; } - return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s #%u", - opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm, - shift_name, shift_amount); + return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s #%u", opname, cond_to_str(cond), sbit_str, + rd_str.c_str(), rn_str.c_str(), rm, shift_name, shift_amount); } -std::string ARM_Disasm::DisassembleBranch(u32 addr, Opcode opcode, u32 insn) -{ +std::string ARM_Disasm::DisassembleBranch(u32 addr, Opcode opcode, u32 insn) { u8 cond = (insn >> 28) & 0xf; u32 offset = insn & 0xffffff; // Sign-extend the 24-bit offset @@ -502,26 +324,23 @@ std::string ARM_Disasm::DisassembleBranch(u32 addr, Opcode opcode, u32 insn) offset <<= 2; offset += 8; addr += offset; - const char *opname = opcode_names[opcode]; + const char* opname = opcode_names[opcode]; return Common::StringFromFormat("%s%s\t0x%x", opname, cond_to_str(cond), addr); } -std::string ARM_Disasm::DisassembleBX(u32 insn) -{ +std::string ARM_Disasm::DisassembleBX(u32 insn) { u8 cond = (insn >> 28) & 0xf; u8 rn = insn & 0xf; return Common::StringFromFormat("bx%s\tr%d", cond_to_str(cond), rn); } -std::string ARM_Disasm::DisassembleBKPT(u32 insn) -{ +std::string ARM_Disasm::DisassembleBKPT(u32 insn) { u8 cond = (insn >> 28) & 0xf; u32 immed = (((insn >> 8) & 0xfff) << 4) | (insn & 0xf); return Common::StringFromFormat("bkpt%s\t#%d", cond_to_str(cond), immed); } -std::string ARM_Disasm::DisassembleCLZ(u32 insn) -{ +std::string ARM_Disasm::DisassembleCLZ(u32 insn) { u8 cond = (insn >> 28) & 0xf; u8 rd = (insn >> 12) & 0xf; u8 rm = insn & 0xf; @@ -545,9 +364,8 @@ std::string ARM_Disasm::DisassembleMediaMulDiv(Opcode opcode, u32 insn) { } std::string ext_reg = ""; - std::unordered_set<Opcode, std::hash<int>> with_ext_reg = { - OP_SMLAD, OP_SMLSD, OP_SMMLA, OP_SMMLS, OP_USADA8 - }; + std::unordered_set<Opcode, std::hash<int>> with_ext_reg = {OP_SMLAD, OP_SMLSD, OP_SMMLA, + OP_SMMLS, OP_USADA8}; if (with_ext_reg.find(opcode) != with_ext_reg.end()) ext_reg = Common::StringFromFormat(", r%u", ra); @@ -560,8 +378,7 @@ std::string ARM_Disasm::DisassembleMediaMulDiv(Opcode opcode, u32 insn) { ext_reg.c_str()); } -std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn) -{ +std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn) { std::string tmp_list; u8 cond = (insn >> 28) & 0xf; @@ -572,17 +389,17 @@ std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn) u8 rn = (insn >> 16) & 0xf; u16 reg_list = insn & 0xffff; - const char *opname = opcode_names[opcode]; + const char* opname = opcode_names[opcode]; - const char *bang = ""; + const char* bang = ""; if (write_back) bang = "!"; - const char *carret = ""; + const char* carret = ""; if (bit_s) carret = "^"; - const char *comma = ""; + const char* comma = ""; tmp_list[0] = 0; for (int ii = 0; ii < 16; ++ii) { if (reg_list & (1 << ii)) { @@ -591,7 +408,7 @@ std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn) } } - const char *addr_mode = ""; + const char* addr_mode = ""; if (is_pre) { if (is_up) { addr_mode = "ib"; @@ -606,12 +423,11 @@ std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn) } } - return Common::StringFromFormat("%s%s%s\tr%d%s, {%s}%s", - opname, cond_to_str(cond), addr_mode, rn, bang, tmp_list.c_str(), carret); + return Common::StringFromFormat("%s%s%s\tr%d%s, {%s}%s", opname, cond_to_str(cond), addr_mode, + rn, bang, tmp_list.c_str(), carret); } -std::string ARM_Disasm::DisassembleMem(u32 insn) -{ +std::string ARM_Disasm::DisassembleMem(u32 insn) { u8 cond = (insn >> 28) & 0xf; u8 is_reg = (insn >> 25) & 0x1; u8 is_load = (insn >> 20) & 0x1; @@ -623,38 +439,40 @@ std::string ARM_Disasm::DisassembleMem(u32 insn) u8 rd = (insn >> 12) & 0xf; u16 offset = insn & 0xfff; - const char *opname = "ldr"; + const char* opname = "ldr"; if (!is_load) opname = "str"; - const char *bang = ""; + const char* bang = ""; if (write_back) bang = "!"; - const char *minus = ""; + const char* minus = ""; if (is_up == 0) minus = "-"; - const char *byte = ""; + const char* byte = ""; if (is_byte) byte = "b"; if (is_reg == 0) { if (is_pre) { if (offset == 0) { - return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", - opname, cond_to_str(cond), byte, rd, rn); + return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", opname, cond_to_str(cond), + byte, rd, rn); } else { - return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", - opname, cond_to_str(cond), byte, rd, rn, minus, offset, bang); + return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", opname, + cond_to_str(cond), byte, rd, rn, minus, offset, + bang); } } else { - const char *transfer = ""; + const char* transfer = ""; if (write_back) transfer = "t"; - return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], #%s%u", - opname, cond_to_str(cond), byte, transfer, rd, rn, minus, offset); + return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], #%s%u", opname, + cond_to_str(cond), byte, transfer, rd, rn, minus, + offset); } } @@ -662,48 +480,47 @@ std::string ARM_Disasm::DisassembleMem(u32 insn) u8 shift_type = (insn >> 5) & 0x3; u8 shift_amount = (insn >> 7) & 0x1f; - const char *shift_name = shift_names[shift_type]; + const char* shift_name = shift_names[shift_type]; if (is_pre) { if (shift_amount == 0) { if (shift_type == 0) { - return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", - opname, cond_to_str(cond), byte, rd, rn, minus, rm, bang); + return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", opname, + cond_to_str(cond), byte, rd, rn, minus, rm, bang); } if (shift_type == 3) { - return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, RRX]%s", - opname, cond_to_str(cond), byte, rd, rn, minus, rm, bang); + return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, RRX]%s", opname, + cond_to_str(cond), byte, rd, rn, minus, rm, bang); } shift_amount = 32; } - return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, %s #%u]%s", - opname, cond_to_str(cond), byte, rd, rn, minus, rm, - shift_name, shift_amount, bang); + return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, %s #%u]%s", opname, + cond_to_str(cond), byte, rd, rn, minus, rm, shift_name, + shift_amount, bang); } - const char *transfer = ""; + const char* transfer = ""; if (write_back) transfer = "t"; if (shift_amount == 0) { if (shift_type == 0) { - return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d", - opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm); + return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d", opname, + cond_to_str(cond), byte, transfer, rd, rn, minus, rm); } if (shift_type == 3) { - return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, RRX", - opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm); + return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, RRX", opname, + cond_to_str(cond), byte, transfer, rd, rn, minus, rm); } shift_amount = 32; } - return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, %s #%u", - opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm, - shift_name, shift_amount); + return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, %s #%u", opname, + cond_to_str(cond), byte, transfer, rd, rn, minus, rm, + shift_name, shift_amount); } -std::string ARM_Disasm::DisassembleMemHalf(u32 insn) -{ +std::string ARM_Disasm::DisassembleMemHalf(u32 insn) { u8 cond = (insn >> 28) & 0xf; u8 is_load = (insn >> 20) & 0x1; u8 write_back = (insn >> 21) & 0x1; @@ -716,11 +533,11 @@ std::string ARM_Disasm::DisassembleMemHalf(u32 insn) u8 rm = insn & 0xf; u8 offset = (((insn >> 8) & 0xf) << 4) | (insn & 0xf); - const char *opname = "ldr"; + const char* opname = "ldr"; if (is_load == 0) opname = "str"; - const char *width = ""; + const char* width = ""; if (bits_65 == 1) width = "h"; else if (bits_65 == 2) @@ -728,38 +545,39 @@ std::string ARM_Disasm::DisassembleMemHalf(u32 insn) else width = "sh"; - const char *bang = ""; + const char* bang = ""; if (write_back) bang = "!"; - const char *minus = ""; + const char* minus = ""; if (is_up == 0) minus = "-"; if (is_immed) { if (is_pre) { if (offset == 0) { - return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", opname, cond_to_str(cond), width, rd, rn); + return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", opname, cond_to_str(cond), + width, rd, rn); } else { - return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", - opname, cond_to_str(cond), width, rd, rn, minus, offset, bang); + return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", opname, + cond_to_str(cond), width, rd, rn, minus, offset, + bang); } } else { - return Common::StringFromFormat("%s%s%s\tr%d, [r%d], #%s%u", - opname, cond_to_str(cond), width, rd, rn, minus, offset); + return Common::StringFromFormat("%s%s%s\tr%d, [r%d], #%s%u", opname, cond_to_str(cond), + width, rd, rn, minus, offset); } } if (is_pre) { - return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", - opname, cond_to_str(cond), width, rd, rn, minus, rm, bang); + return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", opname, cond_to_str(cond), + width, rd, rn, minus, rm, bang); } else { - return Common::StringFromFormat("%s%s%s\tr%d, [r%d], %sr%d", - opname, cond_to_str(cond), width, rd, rn, minus, rm); + return Common::StringFromFormat("%s%s%s\tr%d, [r%d], %sr%d", opname, cond_to_str(cond), + width, rd, rn, minus, rm); } } -std::string ARM_Disasm::DisassembleMCR(Opcode opcode, u32 insn) -{ +std::string ARM_Disasm::DisassembleMCR(Opcode opcode, u32 insn) { u8 cond = (insn >> 28) & 0xf; u8 crn = (insn >> 16) & 0xf; u8 crd = (insn >> 12) & 0xf; @@ -767,13 +585,12 @@ std::string ARM_Disasm::DisassembleMCR(Opcode opcode, u32 insn) u8 opcode2 = (insn >> 5) & 0x7; u8 crm = insn & 0xf; - const char *opname = opcode_names[opcode]; - return Common::StringFromFormat("%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}", - opname, cond_to_str(cond), cpnum, crd, crn, crm, opcode2); + const char* opname = opcode_names[opcode]; + return Common::StringFromFormat("%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}", opname, cond_to_str(cond), + cpnum, crd, crn, crm, opcode2); } -std::string ARM_Disasm::DisassembleMLA(Opcode opcode, u32 insn) -{ +std::string ARM_Disasm::DisassembleMLA(Opcode opcode, u32 insn) { u8 cond = (insn >> 28) & 0xf; u8 rd = (insn >> 16) & 0xf; u8 rn = (insn >> 12) & 0xf; @@ -781,13 +598,12 @@ std::string ARM_Disasm::DisassembleMLA(Opcode opcode, u32 insn) u8 rm = insn & 0xf; u8 bit_s = (insn >> 20) & 1; - const char *opname = opcode_names[opcode]; - return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", - opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs, rn); + const char* opname = opcode_names[opcode]; + return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", opname, cond_to_str(cond), + bit_s ? "s" : "", rd, rm, rs, rn); } -std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, u32 insn) -{ +std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, u32 insn) { u8 cond = (insn >> 28) & 0xf; u8 rdhi = (insn >> 16) & 0xf; u8 rdlo = (insn >> 12) & 0xf; @@ -795,26 +611,24 @@ std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, u32 insn) u8 rm = insn & 0xf; u8 bit_s = (insn >> 20) & 1; - const char *opname = opcode_names[opcode]; - return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", - opname, cond_to_str(cond), bit_s ? "s" : "", rdlo, rdhi, rm, rs); + const char* opname = opcode_names[opcode]; + return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", opname, cond_to_str(cond), + bit_s ? "s" : "", rdlo, rdhi, rm, rs); } -std::string ARM_Disasm::DisassembleMUL(Opcode opcode, u32 insn) -{ +std::string ARM_Disasm::DisassembleMUL(Opcode opcode, u32 insn) { u8 cond = (insn >> 28) & 0xf; u8 rd = (insn >> 16) & 0xf; u8 rs = (insn >> 8) & 0xf; u8 rm = insn & 0xf; u8 bit_s = (insn >> 20) & 1; - const char *opname = opcode_names[opcode]; - return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d", - opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs); + const char* opname = opcode_names[opcode]; + return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d", opname, cond_to_str(cond), + bit_s ? "s" : "", rd, rm, rs); } -std::string ARM_Disasm::DisassembleMRS(u32 insn) -{ +std::string ARM_Disasm::DisassembleMRS(u32 insn) { u8 cond = (insn >> 28) & 0xf; u8 rd = (insn >> 12) & 0xf; u8 ps = (insn >> 22) & 1; @@ -822,8 +636,7 @@ std::string ARM_Disasm::DisassembleMRS(u32 insn) return Common::StringFromFormat("mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr"); } -std::string ARM_Disasm::DisassembleMSR(u32 insn) -{ +std::string ARM_Disasm::DisassembleMSR(u32 insn) { char flags[8]; int flag_index = 0; u8 cond = (insn >> 28) & 0xf; @@ -846,18 +659,17 @@ std::string ARM_Disasm::DisassembleMSR(u32 insn) u8 rotate = (insn >> 8) & 0xf; u8 rotate2 = rotate << 1; u32 rotated_val = (immed >> rotate2) | (immed << (32 - rotate2)); - return Common::StringFromFormat("msr%s\t%s_%s, #0x%x", - cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rotated_val); + return Common::StringFromFormat("msr%s\t%s_%s, #0x%x", cond_to_str(cond), + pd ? "spsr" : "cpsr", flags, rotated_val); } u8 rm = insn & 0xf; - return Common::StringFromFormat("msr%s\t%s_%s, r%d", - cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rm); + return Common::StringFromFormat("msr%s\t%s_%s, r%d", cond_to_str(cond), pd ? "spsr" : "cpsr", + flags, rm); } -std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, u32 insn) -{ +std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, u32 insn) { u32 cond = BITS(insn, 28, 31); return Common::StringFromFormat("%s%s", opcode_names[opcode], cond_to_str(cond)); } @@ -872,8 +684,7 @@ std::string ARM_Disasm::DisassembleParallelAddSub(Opcode opcode, u32 insn) { rd, rn, rm); } -std::string ARM_Disasm::DisassemblePKH(u32 insn) -{ +std::string ARM_Disasm::DisassemblePKH(u32 insn) { u32 cond = BITS(insn, 28, 31); u32 rn = BITS(insn, 16, 19); u32 rd = BITS(insn, 12, 15); @@ -896,13 +707,12 @@ std::string ARM_Disasm::DisassemblePKH(u32 insn) rd, rn, rm, shift.c_str()); } -std::string ARM_Disasm::DisassemblePLD(u32 insn) -{ +std::string ARM_Disasm::DisassemblePLD(u32 insn) { u8 is_reg = (insn >> 25) & 0x1; u8 is_up = (insn >> 23) & 0x1; u8 rn = (insn >> 16) & 0xf; - const char *minus = ""; + const char* minus = ""; if (is_up == 0) minus = "-"; @@ -924,8 +734,8 @@ std::string ARM_Disasm::DisassembleREV(Opcode opcode, u32 insn) { u32 rd = BITS(insn, 12, 15); u32 rm = BITS(insn, 0, 3); - return Common::StringFromFormat("%s%s\tr%u, r%u", opcode_names[opcode], cond_to_str(cond), - rd, rm); + return Common::StringFromFormat("%s%s\tr%u, r%u", opcode_names[opcode], cond_to_str(cond), rd, + rm); } std::string ARM_Disasm::DisassembleREX(Opcode opcode, u32 insn) { @@ -935,26 +745,26 @@ std::string ARM_Disasm::DisassembleREX(Opcode opcode, u32 insn) { u32 cond = BITS(insn, 28, 31); switch (opcode) { - case OP_STREX: - case OP_STREXB: - case OP_STREXH: - return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode], - cond_to_str(cond), rd, rt, rn); - case OP_STREXD: - return Common::StringFromFormat("%s%s\tr%d, r%d, r%d, [r%d]", opcode_names[opcode], - cond_to_str(cond), rd, rt, rt + 1, rn); - - // for LDREX instructions, rd corresponds to Rt from reference manual - case OP_LDREX: - case OP_LDREXB: - case OP_LDREXH: - return Common::StringFromFormat("%s%s\tr%d, [r%d]", opcode_names[opcode], - cond_to_str(cond), rd, rn); - case OP_LDREXD: - return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode], - cond_to_str(cond), rd, rd + 1, rn); - default: - return opcode_names[OP_UNDEFINED]; + case OP_STREX: + case OP_STREXB: + case OP_STREXH: + return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode], + cond_to_str(cond), rd, rt, rn); + case OP_STREXD: + return Common::StringFromFormat("%s%s\tr%d, r%d, r%d, [r%d]", opcode_names[opcode], + cond_to_str(cond), rd, rt, rt + 1, rn); + + // for LDREX instructions, rd corresponds to Rt from reference manual + case OP_LDREX: + case OP_LDREXB: + case OP_LDREXH: + return Common::StringFromFormat("%s%s\tr%d, [r%d]", opcode_names[opcode], cond_to_str(cond), + rd, rn); + case OP_LDREXD: + return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode], + cond_to_str(cond), rd, rd + 1, rn); + default: + return opcode_names[OP_UNDEFINED]; } } @@ -982,8 +792,8 @@ std::string ARM_Disasm::DisassembleSAT(Opcode opcode, u32 insn) { if (opcode == OP_SSAT || opcode == OP_SSAT16) sat_imm++; - return Common::StringFromFormat("%s%s\tr%u, #%u, r%u%s", opcode_names[opcode], cond_to_str(cond), rd, - sat_imm, rn, shift_part.c_str()); + return Common::StringFromFormat("%s%s\tr%u, #%u, r%u%s", opcode_names[opcode], + cond_to_str(cond), rd, sat_imm, rn, shift_part.c_str()); } std::string ARM_Disasm::DisassembleSEL(u32 insn) { @@ -996,27 +806,24 @@ std::string ARM_Disasm::DisassembleSEL(u32 insn) { rd, rn, rm); } -std::string ARM_Disasm::DisassembleSWI(u32 insn) -{ +std::string ARM_Disasm::DisassembleSWI(u32 insn) { u8 cond = (insn >> 28) & 0xf; u32 sysnum = insn & 0x00ffffff; return Common::StringFromFormat("swi%s 0x%x", cond_to_str(cond), sysnum); } -std::string ARM_Disasm::DisassembleSWP(Opcode opcode, u32 insn) -{ +std::string ARM_Disasm::DisassembleSWP(Opcode opcode, u32 insn) { u8 cond = (insn >> 28) & 0xf; u8 rn = (insn >> 16) & 0xf; u8 rd = (insn >> 12) & 0xf; u8 rm = insn & 0xf; - const char *opname = opcode_names[opcode]; + const char* opname = opcode_names[opcode]; return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn); } -std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn) -{ +std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn) { u32 cond = BITS(insn, 28, 31); u32 rn = BITS(insn, 16, 19); u32 rd = BITS(insn, 12, 15); @@ -1025,9 +832,7 @@ std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn) std::string rn_part = ""; static std::unordered_set<Opcode, std::hash<int>> extend_with_add = { - OP_SXTAB, OP_SXTAB16, OP_SXTAH, - OP_UXTAB, OP_UXTAB16, OP_UXTAH - }; + OP_SXTAB, OP_SXTAB16, OP_SXTAH, OP_UXTAB, OP_UXTAB16, OP_UXTAH}; if (extend_with_add.find(opcode) != extend_with_add.end()) rn_part = ", r" + std::to_string(rn); @@ -1042,14 +847,14 @@ std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn) Opcode ARM_Disasm::Decode(u32 insn) { u32 bits27_26 = (insn >> 26) & 0x3; switch (bits27_26) { - case 0x0: - return Decode00(insn); - case 0x1: - return Decode01(insn); - case 0x2: - return Decode10(insn); - case 0x3: - return Decode11(insn); + case 0x0: + return Decode00(insn); + case 0x1: + return Decode01(insn); + case 0x2: + return Decode10(insn); + case 0x3: + return Decode11(insn); } return OP_INVALID; } @@ -1198,28 +1003,28 @@ Opcode ARM_Disasm::DecodeSyncPrimitive(u32 insn) { u32 op = BITS(insn, 20, 23); u32 bit22 = BIT(insn, 22); switch (op) { - case 0x0: - if (bit22) - return OP_SWPB; - return OP_SWP; - case 0x8: - return OP_STREX; - case 0x9: - return OP_LDREX; - case 0xA: - return OP_STREXD; - case 0xB: - return OP_LDREXD; - case 0xC: - return OP_STREXB; - case 0xD: - return OP_LDREXB; - case 0xE: - return OP_STREXH; - case 0xF: - return OP_LDREXH; - default: - return OP_UNDEFINED; + case 0x0: + if (bit22) + return OP_SWPB; + return OP_SWP; + case 0x8: + return OP_STREX; + case 0x9: + return OP_LDREX; + case 0xA: + return OP_STREXD; + case 0xB: + return OP_LDREXD; + case 0xC: + return OP_STREXB; + case 0xD: + return OP_LDREXB; + case 0xE: + return OP_STREXH; + case 0xF: + return OP_LDREXH; + default: + return OP_UNDEFINED; } } @@ -1240,27 +1045,14 @@ Opcode ARM_Disasm::DecodeParallelAddSub(u32 insn) { static std::vector<Opcode> opcodes = { // op1 = 0 - OP_SADD16, OP_UADD16, - OP_SASX, OP_UASX, - OP_SSAX, OP_USAX, - OP_SSUB16, OP_USUB16, - OP_SADD8, OP_UADD8, - OP_SSUB8, OP_USUB8, + OP_SADD16, OP_UADD16, OP_SASX, OP_UASX, OP_SSAX, OP_USAX, OP_SSUB16, OP_USUB16, OP_SADD8, + OP_UADD8, OP_SSUB8, OP_USUB8, // op1 = 1 - OP_QADD16, OP_UQADD16, - OP_QASX, OP_UQASX, - OP_QSAX, OP_UQSAX, - OP_QSUB16, OP_UQSUB16, - OP_QADD8, OP_UQADD8, - OP_QSUB8, OP_UQSUB8, + OP_QADD16, OP_UQADD16, OP_QASX, OP_UQASX, OP_QSAX, OP_UQSAX, OP_QSUB16, OP_UQSUB16, + OP_QADD8, OP_UQADD8, OP_QSUB8, OP_UQSUB8, // op1 = 2 - OP_SHADD16, OP_UHADD16, - OP_SHASX, OP_UHASX, - OP_SHSAX, OP_UHSAX, - OP_SHSUB16, OP_UHSUB16, - OP_SHADD8, OP_UHADD8, - OP_SHSUB8, OP_UHSUB8 - }; + OP_SHADD16, OP_UHADD16, OP_SHASX, OP_UHASX, OP_SHSAX, OP_UHSAX, OP_SHSUB16, OP_UHSUB16, + OP_SHADD8, OP_UHADD8, OP_SHSUB8, OP_UHSUB8}; u32 opcode_index = op1 * 12 + op2 * 2 + is_unsigned; return opcodes[opcode_index]; @@ -1272,66 +1064,66 @@ Opcode ARM_Disasm::DecodePackingSaturationReversal(u32 insn) { u32 op2 = BITS(insn, 5, 7); switch (op1) { - case 0x0: - if (BIT(op2, 0) == 0) - return OP_PKH; - if (op2 == 0x3 && a != 0xf) - return OP_SXTAB16; - if (op2 == 0x3 && a == 0xf) - return OP_SXTB16; - if (op2 == 0x5) - return OP_SEL; - break; - case 0x2: - if (BIT(op2, 0) == 0) - return OP_SSAT; - if (op2 == 0x1) - return OP_SSAT16; - if (op2 == 0x3 && a != 0xf) - return OP_SXTAB; - if (op2 == 0x3 && a == 0xf) - return OP_SXTB; - break; - case 0x3: - if (op2 == 0x1) - return OP_REV; - if (BIT(op2, 0) == 0) - return OP_SSAT; - if (op2 == 0x3 && a != 0xf) - return OP_SXTAH; - if (op2 == 0x3 && a == 0xf) - return OP_SXTH; - if (op2 == 0x5) - return OP_REV16; - break; - case 0x4: - if (op2 == 0x3 && a != 0xf) - return OP_UXTAB16; - if (op2 == 0x3 && a == 0xf) - return OP_UXTB16; - break; - case 0x6: - if (BIT(op2, 0) == 0) - return OP_USAT; - if (op2 == 0x1) - return OP_USAT16; - if (op2 == 0x3 && a != 0xf) - return OP_UXTAB; - if (op2 == 0x3 && a == 0xf) - return OP_UXTB; - break; - case 0x7: - if (BIT(op2, 0) == 0) - return OP_USAT; - if (op2 == 0x3 && a != 0xf) - return OP_UXTAH; - if (op2 == 0x3 && a == 0xf) - return OP_UXTH; - if (op2 == 0x5) - return OP_REVSH; - break; - default: - break; + case 0x0: + if (BIT(op2, 0) == 0) + return OP_PKH; + if (op2 == 0x3 && a != 0xf) + return OP_SXTAB16; + if (op2 == 0x3 && a == 0xf) + return OP_SXTB16; + if (op2 == 0x5) + return OP_SEL; + break; + case 0x2: + if (BIT(op2, 0) == 0) + return OP_SSAT; + if (op2 == 0x1) + return OP_SSAT16; + if (op2 == 0x3 && a != 0xf) + return OP_SXTAB; + if (op2 == 0x3 && a == 0xf) + return OP_SXTB; + break; + case 0x3: + if (op2 == 0x1) + return OP_REV; + if (BIT(op2, 0) == 0) + return OP_SSAT; + if (op2 == 0x3 && a != 0xf) + return OP_SXTAH; + if (op2 == 0x3 && a == 0xf) + return OP_SXTH; + if (op2 == 0x5) + return OP_REV16; + break; + case 0x4: + if (op2 == 0x3 && a != 0xf) + return OP_UXTAB16; + if (op2 == 0x3 && a == 0xf) + return OP_UXTB16; + break; + case 0x6: + if (BIT(op2, 0) == 0) + return OP_USAT; + if (op2 == 0x1) + return OP_USAT16; + if (op2 == 0x3 && a != 0xf) + return OP_UXTAB; + if (op2 == 0x3 && a == 0xf) + return OP_UXTB; + break; + case 0x7: + if (BIT(op2, 0) == 0) + return OP_USAT; + if (op2 == 0x3 && a != 0xf) + return OP_UXTAH; + if (op2 == 0x3 && a == 0xf) + return OP_UXTH; + if (op2 == 0x5) + return OP_REVSH; + break; + default: + break; } return OP_UNDEFINED; @@ -1378,18 +1170,18 @@ Opcode ARM_Disasm::DecodeMSRImmAndHints(u32 insn) { if (op == 0 && op1 == 0) { switch (op2) { - case 0x0: - return OP_NOP; - case 0x1: - return OP_YIELD; - case 0x2: - return OP_WFE; - case 0x3: - return OP_WFI; - case 0x4: - return OP_SEV; - default: - return OP_UNDEFINED; + case 0x0: + return OP_NOP; + case 0x1: + return OP_YIELD; + case 0x2: + return OP_WFE; + case 0x3: + return OP_WFI; + case 0x4: + return OP_SEV; + default: + return OP_UNDEFINED; } } @@ -1402,37 +1194,37 @@ Opcode ARM_Disasm::DecodeMediaMulDiv(u32 insn) { u32 a = BITS(insn, 12, 15); switch (op1) { - case 0x0: - if (op2_h == 0x0) { - if (a != 0xf) - return OP_SMLAD; - else - return OP_SMUAD; - } else if (op2_h == 0x1) { - if (a != 0xf) - return OP_SMLSD; - else - return OP_SMUSD; - } - break; - case 0x4: - if (op2_h == 0x0) - return OP_SMLALD; - else if (op2_h == 0x1) - return OP_SMLSLD; - break; - case 0x5: - if (op2_h == 0x0) { - if (a != 0xf) - return OP_SMMLA; - else - return OP_SMMUL; - } else if (op2_h == 0x3) { - return OP_SMMLS; - } - break; - default: - break; + case 0x0: + if (op2_h == 0x0) { + if (a != 0xf) + return OP_SMLAD; + else + return OP_SMUAD; + } else if (op2_h == 0x1) { + if (a != 0xf) + return OP_SMLSD; + else + return OP_SMUSD; + } + break; + case 0x4: + if (op2_h == 0x0) + return OP_SMLALD; + else if (op2_h == 0x1) + return OP_SMLSLD; + break; + case 0x5: + if (op2_h == 0x0) { + if (a != 0xf) + return OP_SMMLA; + else + return OP_SMMUL; + } else if (op2_h == 0x3) { + return OP_SMMLS; + } + break; + default: + break; } return OP_UNDEFINED; @@ -1444,23 +1236,23 @@ Opcode ARM_Disasm::DecodeMedia(u32 insn) { u32 op2 = BITS(insn, 5, 7); switch (BITS(op1, 3, 4)) { - case 0x0: - // unsigned and signed parallel addition and subtraction - return DecodeParallelAddSub(insn); - case 0x1: - // Packing, unpacking, saturation, and reversal - return DecodePackingSaturationReversal(insn); - case 0x2: - // Signed multiply, signed and unsigned divide - return DecodeMediaMulDiv(insn); - case 0x3: - if (op2 == 0 && rd == 0xf) - return OP_USAD8; - if (op2 == 0 && rd != 0xf) - return OP_USADA8; - break; - default: - break; + case 0x0: + // unsigned and signed parallel addition and subtraction + return DecodeParallelAddSub(insn); + case 0x1: + // Packing, unpacking, saturation, and reversal + return DecodePackingSaturationReversal(insn); + case 0x2: + // Signed multiply, signed and unsigned divide + return DecodeMediaMulDiv(insn); + case 0x3: + if (op2 == 0 && rd == 0xf) + return OP_USAD8; + if (op2 == 0 && rd != 0xf) + return OP_USADA8; + break; + default: + break; } return OP_UNDEFINED; @@ -1508,46 +1300,46 @@ Opcode ARM_Disasm::DecodeALU(u32 insn) { return OP_UNDEFINED; } switch (opcode) { - case 0x0: - return OP_AND; - case 0x1: - return OP_EOR; - case 0x2: - return OP_SUB; - case 0x3: - return OP_RSB; - case 0x4: - return OP_ADD; - case 0x5: - return OP_ADC; - case 0x6: - return OP_SBC; - case 0x7: - return OP_RSC; - case 0x8: - if (bit_s) - return OP_TST; - return OP_MRS; - case 0x9: - if (bit_s) - return OP_TEQ; - return OP_MSR; - case 0xa: - if (bit_s) - return OP_CMP; - return OP_MRS; - case 0xb: - if (bit_s) - return OP_CMN; - return OP_MSR; - case 0xc: - return OP_ORR; - case 0xd: - return OP_MOV; - case 0xe: - return OP_BIC; - case 0xf: - return OP_MVN; + case 0x0: + return OP_AND; + case 0x1: + return OP_EOR; + case 0x2: + return OP_SUB; + case 0x3: + return OP_RSB; + case 0x4: + return OP_ADD; + case 0x5: + return OP_ADC; + case 0x6: + return OP_SBC; + case 0x7: + return OP_RSC; + case 0x8: + if (bit_s) + return OP_TST; + return OP_MRS; + case 0x9: + if (bit_s) + return OP_TEQ; + return OP_MSR; + case 0xa: + if (bit_s) + return OP_CMP; + return OP_MRS; + case 0xb: + if (bit_s) + return OP_CMN; + return OP_MSR; + case 0xc: + return OP_ORR; + case 0xd: + return OP_MOV; + case 0xe: + return OP_BIC; + case 0xf: + return OP_MVN; } // Unreachable return OP_INVALID; diff --git a/src/core/arm/disassembler/arm_disasm.h b/src/core/arm/disassembler/arm_disasm.h index 53d9c6a74..031f973d6 100644 --- a/src/core/arm/disassembler/arm_disasm.h +++ b/src/core/arm/disassembler/arm_disasm.h @@ -187,53 +187,53 @@ enum Opcode { OP_THUMB_SWI, OP_THUMB_TST, - OP_END // must be last + OP_END // must be last }; class ARM_Disasm { - public: - static std::string Disassemble(u32 addr, u32 insn); - static Opcode Decode(u32 insn); +public: + static std::string Disassemble(u32 addr, u32 insn); + static Opcode Decode(u32 insn); - private: - static Opcode Decode00(u32 insn); - static Opcode Decode01(u32 insn); - static Opcode Decode10(u32 insn); - static Opcode Decode11(u32 insn); - static Opcode DecodeSyncPrimitive(u32 insn); - static Opcode DecodeParallelAddSub(u32 insn); - static Opcode DecodePackingSaturationReversal(u32 insn); - static Opcode DecodeMUL(u32 insn); - static Opcode DecodeMSRImmAndHints(u32 insn); - static Opcode DecodeMediaMulDiv(u32 insn); - static Opcode DecodeMedia(u32 insn); - static Opcode DecodeLDRH(u32 insn); - static Opcode DecodeALU(u32 insn); +private: + static Opcode Decode00(u32 insn); + static Opcode Decode01(u32 insn); + static Opcode Decode10(u32 insn); + static Opcode Decode11(u32 insn); + static Opcode DecodeSyncPrimitive(u32 insn); + static Opcode DecodeParallelAddSub(u32 insn); + static Opcode DecodePackingSaturationReversal(u32 insn); + static Opcode DecodeMUL(u32 insn); + static Opcode DecodeMSRImmAndHints(u32 insn); + static Opcode DecodeMediaMulDiv(u32 insn); + static Opcode DecodeMedia(u32 insn); + static Opcode DecodeLDRH(u32 insn); + static Opcode DecodeALU(u32 insn); - static std::string DisassembleALU(Opcode opcode, u32 insn); - static std::string DisassembleBranch(u32 addr, Opcode opcode, u32 insn); - static std::string DisassembleBX(u32 insn); - static std::string DisassembleBKPT(u32 insn); - static std::string DisassembleCLZ(u32 insn); - static std::string DisassembleMediaMulDiv(Opcode opcode, u32 insn); - static std::string DisassembleMemblock(Opcode opcode, u32 insn); - static std::string DisassembleMem(u32 insn); - static std::string DisassembleMemHalf(u32 insn); - static std::string DisassembleMCR(Opcode opcode, u32 insn); - static std::string DisassembleMLA(Opcode opcode, u32 insn); - static std::string DisassembleUMLAL(Opcode opcode, u32 insn); - static std::string DisassembleMUL(Opcode opcode, u32 insn); - static std::string DisassembleMRS(u32 insn); - static std::string DisassembleMSR(u32 insn); - static std::string DisassembleNoOperands(Opcode opcode, u32 insn); - static std::string DisassembleParallelAddSub(Opcode opcode, u32 insn); - static std::string DisassemblePKH(u32 insn); - static std::string DisassemblePLD(u32 insn); - static std::string DisassembleREV(Opcode opcode, u32 insn); - static std::string DisassembleREX(Opcode opcode, u32 insn); - static std::string DisassembleSAT(Opcode opcode, u32 insn); - static std::string DisassembleSEL(u32 insn); - static std::string DisassembleSWI(u32 insn); - static std::string DisassembleSWP(Opcode opcode, u32 insn); - static std::string DisassembleXT(Opcode opcode, u32 insn); + static std::string DisassembleALU(Opcode opcode, u32 insn); + static std::string DisassembleBranch(u32 addr, Opcode opcode, u32 insn); + static std::string DisassembleBX(u32 insn); + static std::string DisassembleBKPT(u32 insn); + static std::string DisassembleCLZ(u32 insn); + static std::string DisassembleMediaMulDiv(Opcode opcode, u32 insn); + static std::string DisassembleMemblock(Opcode opcode, u32 insn); + static std::string DisassembleMem(u32 insn); + static std::string DisassembleMemHalf(u32 insn); + static std::string DisassembleMCR(Opcode opcode, u32 insn); + static std::string DisassembleMLA(Opcode opcode, u32 insn); + static std::string DisassembleUMLAL(Opcode opcode, u32 insn); + static std::string DisassembleMUL(Opcode opcode, u32 insn); + static std::string DisassembleMRS(u32 insn); + static std::string DisassembleMSR(u32 insn); + static std::string DisassembleNoOperands(Opcode opcode, u32 insn); + static std::string DisassembleParallelAddSub(Opcode opcode, u32 insn); + static std::string DisassemblePKH(u32 insn); + static std::string DisassemblePLD(u32 insn); + static std::string DisassembleREV(Opcode opcode, u32 insn); + static std::string DisassembleREX(Opcode opcode, u32 insn); + static std::string DisassembleSAT(Opcode opcode, u32 insn); + static std::string DisassembleSEL(u32 insn); + static std::string DisassembleSWI(u32 insn); + static std::string DisassembleSWP(Opcode opcode, u32 insn); + static std::string DisassembleXT(Opcode opcode, u32 insn); }; diff --git a/src/core/arm/disassembler/load_symbol_map.cpp b/src/core/arm/disassembler/load_symbol_map.cpp index eb20bf6f7..58e8e6fa1 100644 --- a/src/core/arm/disassembler/load_symbol_map.cpp +++ b/src/core/arm/disassembler/load_symbol_map.cpp @@ -6,8 +6,8 @@ #include <string> #include <vector> -#include "common/symbols.h" #include "common/file_util.h" +#include "common/symbols.h" #include "core/arm/disassembler/load_symbol_map.h" diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp index 6dbc92b91..64dcaae08 100644 --- a/src/core/arm/dyncom/arm_dyncom_dec.cpp +++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp @@ -430,12 +430,15 @@ ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx) { continue; while (n) { - if (arm_instruction[i].content[base + 1] == 31 && arm_instruction[i].content[base] == 0) { + if (arm_instruction[i].content[base + 1] == 31 && + arm_instruction[i].content[base] == 0) { // clrex if (instr != arm_instruction[i].content[base + 2]) { break; } - } else if (BITS(instr, arm_instruction[i].content[base], arm_instruction[i].content[base + 1]) != arm_instruction[i].content[base + 2]) { + } else if (BITS(instr, arm_instruction[i].content[base], + arm_instruction[i].content[base + 1]) != + arm_instruction[i].content[base + 2]) { break; } base += 3; @@ -451,7 +454,9 @@ ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx) { if (n != 0) { base = 0; while (n) { - if (BITS(instr, arm_exclusion_code[i].content[base], arm_exclusion_code[i].content[base + 1]) != arm_exclusion_code[i].content[base + 2]) { + if (BITS(instr, arm_exclusion_code[i].content[base], + arm_exclusion_code[i].content[base + 1]) != + arm_exclusion_code[i].content[base + 2]) { break; } base += 3; diff --git a/src/core/arm/dyncom/arm_dyncom_dec.h b/src/core/arm/dyncom/arm_dyncom_dec.h index d7170e0fc..2fb7ac37c 100644 --- a/src/core/arm/dyncom/arm_dyncom_dec.h +++ b/src/core/arm/dyncom/arm_dyncom_dec.h @@ -6,15 +6,12 @@ #include "common/common_types.h" -enum class ARMDecodeStatus { - SUCCESS, - FAILURE -}; +enum class ARMDecodeStatus { SUCCESS, FAILURE }; ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx); struct InstructionSetEncodingItem { - const char *name; + const char* name; int attribute_value; int version; u32 content[21]; diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index c8d45c6db..211d49edb 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -11,29 +11,29 @@ #include "common/logging/log.h" #include "common/microprofile.h" -#include "core/memory.h" -#include "core/hle/svc.h" #include "core/arm/disassembler/arm_disasm.h" #include "core/arm/dyncom/arm_dyncom_dec.h" #include "core/arm/dyncom/arm_dyncom_interpreter.h" +#include "core/arm/dyncom/arm_dyncom_run.h" #include "core/arm/dyncom/arm_dyncom_thumb.h" #include "core/arm/dyncom/arm_dyncom_trans.h" -#include "core/arm/dyncom/arm_dyncom_run.h" #include "core/arm/skyeye_common/armstate.h" #include "core/arm/skyeye_common/armsupp.h" #include "core/arm/skyeye_common/vfp/vfp.h" +#include "core/hle/svc.h" +#include "core/memory.h" #include "core/gdbstub/gdbstub.h" -#define RM BITS(sht_oper, 0, 3) -#define RS BITS(sht_oper, 8, 11) +#define RM BITS(sht_oper, 0, 3) +#define RS BITS(sht_oper, 8, 11) -#define glue(x, y) x ## y -#define DPO(s) glue(DataProcessingOperands, s) +#define glue(x, y) x##y +#define DPO(s) glue(DataProcessingOperands, s) #define ROTATE_RIGHT(n, i, l) ((n << (l - i)) | (n >> i)) -#define ROTATE_LEFT(n, i, l) ((n >> (l - i)) | (n << i)) +#define ROTATE_LEFT(n, i, l) ((n >> (l - i)) | (n << i)) #define ROTATE_RIGHT_32(n, i) ROTATE_RIGHT(n, i, 32) -#define ROTATE_LEFT_32(n, i) ROTATE_LEFT(n, i, 32) +#define ROTATE_LEFT_32(n, i) ROTATE_LEFT(n, i, 32) static bool CondPassed(const ARMul_State* cpu, unsigned int cond) { const bool n_flag = cpu->NFlag != 0; @@ -232,17 +232,19 @@ static unsigned int DPO(RotateRightByRegister)(ARMul_State* cpu, unsigned int sh return shifter_operand; } -#define DEBUG_MSG LOG_DEBUG(Core_ARM11, "inst is %x", inst); CITRA_IGNORE_EXIT(0) +#define DEBUG_MSG \ + LOG_DEBUG(Core_ARM11, "inst is %x", inst); \ + CITRA_IGNORE_EXIT(0) -#define LnSWoUB(s) glue(LnSWoUB, s) -#define MLnS(s) glue(MLnS, s) -#define LdnStM(s) glue(LdnStM, s) +#define LnSWoUB(s) glue(LnSWoUB, s) +#define MLnS(s) glue(MLnS, s) +#define LdnStM(s) glue(LdnStM, s) -#define W_BIT BIT(inst, 21) -#define U_BIT BIT(inst, 23) -#define I_BIT BIT(inst, 25) -#define P_BIT BIT(inst, 24) -#define OFFSET_12 BITS(inst, 0, 11) +#define W_BIT BIT(inst, 21) +#define U_BIT BIT(inst, 23) +#define I_BIT BIT(inst, 25) +#define P_BIT BIT(inst, 24) +#define OFFSET_12 BITS(inst, 0, 11) static void LnSWoUB(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { unsigned int Rn = BITS(inst, 16, 19); @@ -271,7 +273,8 @@ static void LnSWoUB(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigne virt_addr = addr; } -static void LnSWoUB(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { +static void LnSWoUB(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, + unsigned int& virt_addr) { unsigned int Rn = BITS(inst, 16, 19); unsigned int addr = CHECK_READ_REG15_WA(cpu, Rn); @@ -283,7 +286,8 @@ static void LnSWoUB(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, u virt_addr = addr; } -static void LnSWoUB(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { +static void LnSWoUB(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, + unsigned int& virt_addr) { unsigned int Rn = BITS(inst, 16, 19); unsigned int addr; @@ -301,7 +305,7 @@ static void LnSWoUB(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, un static void MLnS(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { unsigned int addr; unsigned int Rn = BITS(inst, 16, 19); - unsigned int Rm = BITS(inst, 0, 3); + unsigned int Rm = BITS(inst, 0, 3); unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); @@ -316,7 +320,8 @@ static void MLnS(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsign cpu->Reg[Rn] = addr; } -static void LnSWoUB(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { +static void LnSWoUB(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, + unsigned int& virt_addr) { unsigned int Rn = BITS(inst, 16, 19); unsigned int Rm = BITS(inst, 0, 3); unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); @@ -335,7 +340,8 @@ static void LnSWoUB(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, uns } } -static void LnSWoUB(ScaledRegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { +static void LnSWoUB(ScaledRegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, + unsigned int& virt_addr) { unsigned int shift = BITS(inst, 5, 6); unsigned int shift_imm = BITS(inst, 7, 11); unsigned int Rn = BITS(inst, 16, 19); @@ -386,7 +392,8 @@ static void LnSWoUB(ScaledRegisterPreIndexed)(ARMul_State* cpu, unsigned int ins cpu->Reg[Rn] = addr; } -static void LnSWoUB(ScaledRegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { +static void LnSWoUB(ScaledRegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, + unsigned int& virt_addr) { unsigned int shift = BITS(inst, 5, 6); unsigned int shift_imm = BITS(inst, 7, 11); unsigned int Rn = BITS(inst, 16, 19); @@ -435,9 +442,10 @@ static void LnSWoUB(ScaledRegisterPostIndexed)(ARMul_State* cpu, unsigned int in } } -static void LnSWoUB(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { +static void LnSWoUB(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, + unsigned int& virt_addr) { unsigned int Rn = BITS(inst, 16, 19); - unsigned int Rm = BITS(inst, 0, 3); + unsigned int Rm = BITS(inst, 0, 3); unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); virt_addr = CHECK_READ_REG15_WA(cpu, Rn); @@ -454,7 +462,7 @@ static void LnSWoUB(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, un static void MLnS(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { unsigned int immedL = BITS(inst, 0, 3); unsigned int immedH = BITS(inst, 8, 11); - unsigned int Rn = BITS(inst, 16, 19); + unsigned int Rn = BITS(inst, 16, 19); unsigned int addr; unsigned int offset_8 = (immedH << 4) | immedL; @@ -470,7 +478,7 @@ static void MLnS(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned static void MLnS(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { unsigned int addr; unsigned int Rn = BITS(inst, 16, 19); - unsigned int Rm = BITS(inst, 0, 3); + unsigned int Rm = BITS(inst, 0, 3); unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); @@ -482,10 +490,11 @@ static void MLnS(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned i virt_addr = addr; } -static void MLnS(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { - unsigned int Rn = BITS(inst, 16, 19); - unsigned int immedH = BITS(inst, 8, 11); - unsigned int immedL = BITS(inst, 0, 3); +static void MLnS(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, + unsigned int& virt_addr) { + unsigned int Rn = BITS(inst, 16, 19); + unsigned int immedH = BITS(inst, 8, 11); + unsigned int immedL = BITS(inst, 0, 3); unsigned int addr; unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); unsigned int offset_8 = (immedH << 4) | immedL; @@ -501,10 +510,11 @@ static void MLnS(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsig cpu->Reg[Rn] = addr; } -static void MLnS(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { - unsigned int Rn = BITS(inst, 16, 19); - unsigned int immedH = BITS(inst, 8, 11); - unsigned int immedL = BITS(inst, 0, 3); +static void MLnS(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, + unsigned int& virt_addr) { + unsigned int Rn = BITS(inst, 16, 19); + unsigned int immedH = BITS(inst, 8, 11); + unsigned int immedL = BITS(inst, 0, 3); unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); virt_addr = rn; @@ -520,9 +530,10 @@ static void MLnS(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsi } } -static void MLnS(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { +static void MLnS(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, + unsigned int& virt_addr) { unsigned int Rn = BITS(inst, 16, 19); - unsigned int Rm = BITS(inst, 0, 3); + unsigned int Rm = BITS(inst, 0, 3); unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); virt_addr = CHECK_READ_REG15_WA(cpu, Rn); @@ -541,7 +552,8 @@ static void LdnStM(DecrementBefore)(ARMul_State* cpu, unsigned int inst, unsigne int count = 0; while (i) { - if (i & 1) count++; + if (i & 1) + count++; i = i >> 1; } @@ -557,7 +569,8 @@ static void LdnStM(IncrementBefore)(ARMul_State* cpu, unsigned int inst, unsigne int count = 0; while (i) { - if (i & 1) count++; + if (i & 1) + count++; i = i >> 1; } @@ -572,8 +585,9 @@ static void LdnStM(IncrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned unsigned int i = BITS(inst, 0, 15); int count = 0; - while(i) { - if (i & 1) count++; + while (i) { + if (i & 1) + count++; i = i >> 1; } @@ -587,8 +601,9 @@ static void LdnStM(DecrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned unsigned int Rn = BITS(inst, 16, 19); unsigned int i = BITS(inst, 0, 15); int count = 0; - while(i) { - if(i & 1) count++; + while (i) { + if (i & 1) + count++; i = i >> 1; } unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); @@ -601,7 +616,8 @@ static void LdnStM(DecrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned } } -static void LnSWoUB(ScaledRegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { +static void LnSWoUB(ScaledRegisterOffset)(ARMul_State* cpu, unsigned int inst, + unsigned int& virt_addr) { unsigned int shift = BITS(inst, 5, 6); unsigned int shift_imm = BITS(inst, 7, 11); unsigned int Rn = BITS(inst, 16, 19); @@ -693,17 +709,23 @@ get_addr_fp_t GetAddressingOp(unsigned int inst) { return LnSWoUB(RegisterPostIndexed); } else if (BITS(inst, 24, 27) == 6 && BIT(inst, 21) == 0 && BIT(inst, 4) == 0) { return LnSWoUB(ScaledRegisterPostIndexed); - } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 2 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { + } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 2 && BIT(inst, 7) == 1 && + BIT(inst, 4) == 1) { return MLnS(ImmediateOffset); - } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 0 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { + } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 0 && BIT(inst, 7) == 1 && + BIT(inst, 4) == 1) { return MLnS(RegisterOffset); - } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 3 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { + } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 3 && BIT(inst, 7) == 1 && + BIT(inst, 4) == 1) { return MLnS(ImmediatePreIndexed); - } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 1 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { + } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 1 && BIT(inst, 7) == 1 && + BIT(inst, 4) == 1) { return MLnS(RegisterPreIndexed); - } else if (BITS(inst, 24, 27) == 0 && BITS(inst, 21, 22) == 2 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { + } else if (BITS(inst, 24, 27) == 0 && BITS(inst, 21, 22) == 2 && BIT(inst, 7) == 1 && + BIT(inst, 4) == 1) { return MLnS(ImmediatePostIndexed); - } else if (BITS(inst, 24, 27) == 0 && BITS(inst, 21, 22) == 0 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { + } else if (BITS(inst, 24, 27) == 0 && BITS(inst, 21, 22) == 0 && BIT(inst, 7) == 1 && + BIT(inst, 4) == 1) { return MLnS(RegisterPostIndexed); } else if (BITS(inst, 23, 27) == 0x11) { return LdnStM(IncrementAfter); @@ -732,14 +754,12 @@ get_addr_fp_t GetAddressingOpLoadStoreT(unsigned int inst) { return nullptr; } -enum { - FETCH_SUCCESS, - FETCH_FAILURE -}; +enum { FETCH_SUCCESS, FETCH_FAILURE }; -static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_inst, u32* inst_size, ARM_INST_PTR* ptr_inst_base) { +static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_inst, u32* inst_size, + ARM_INST_PTR* ptr_inst_base) { // Check if in Thumb mode - ThumbDecodeStatus ret = TranslateThumbInstruction (addr, inst, arm_inst, inst_size); + ThumbDecodeStatus ret = TranslateThumbInstruction(addr, inst, arm_inst, inst_size); if (ret == ThumbDecodeStatus::BRANCH) { int inst_index; int table_length = arm_instruction_trans_len; @@ -748,7 +768,7 @@ static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_ins switch ((tinstr & 0xF800) >> 11) { case 26: case 27: - if (((tinstr & 0x0F00) != 0x0E00) && ((tinstr & 0x0F00) != 0x0F00)){ + if (((tinstr & 0x0F00) != 0x0E00) && ((tinstr & 0x0F00) != 0x0F00)) { inst_index = table_length - 4; *ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index); } else { @@ -785,21 +805,21 @@ static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_ins return ret; } -enum { - KEEP_GOING, - FETCH_EXCEPTION -}; +enum { KEEP_GOING, FETCH_EXCEPTION }; MICROPROFILE_DEFINE(DynCom_Decode, "DynCom", "Decode", MP_RGB(255, 64, 64)); -static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, const u32 phys_addr, ARM_INST_PTR& inst_base) { +static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, const u32 phys_addr, + ARM_INST_PTR& inst_base) { unsigned int inst_size = 4; unsigned int inst = Memory::Read32(phys_addr & 0xFFFFFFFC); - // If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM instruction + // If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM + // instruction if (cpu->TFlag) { u32 arm_inst; - ThumbDecodeStatus state = DecodeThumbInstruction(inst, phys_addr, &arm_inst, &inst_size, &inst_base); + ThumbDecodeStatus state = + DecodeThumbInstruction(inst, phys_addr, &arm_inst, &inst_size, &inst_base); // We have translated the Thumb branch instruction in the Thumb decoder if (state == ThumbDecodeStatus::BRANCH) { @@ -811,8 +831,10 @@ static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, cons int idx; if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) { std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst); - LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, disasm.c_str(), inst); - LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag, cpu->Reg[15]); + LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, + disasm.c_str(), inst); + LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag, + cpu->Reg[15]); CITRA_IGNORE_EXIT(-1); } inst_base = arm_instruction_trans[idx](inst, idx); @@ -875,12 +897,25 @@ static int InterpreterTranslateSingle(ARMul_State* cpu, int& bb_start, u32 addr) static int clz(unsigned int x) { int n; - if (x == 0) return (32); + if (x == 0) + return (32); n = 1; - if ((x >> 16) == 0) { n = n + 16; x = x << 16;} - if ((x >> 24) == 0) { n = n + 8; x = x << 8;} - if ((x >> 28) == 0) { n = n + 4; x = x << 4;} - if ((x >> 30) == 0) { n = n + 2; x = x << 2;} + if ((x >> 16) == 0) { + n = n + 16; + x = x << 16; + } + if ((x >> 24) == 0) { + n = n + 8; + x = x << 8; + } + if ((x >> 28) == 0) { + n = n + 4; + x = x << 4; + } + if ((x >> 30) == 0) { + n = n + 2; + x = x << 2; + } n = n - (x >> 31); return n; } @@ -892,310 +927,698 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { GDBStub::BreakpointAddress breakpoint_data; - #undef RM - #undef RS - - #define CRn inst_cream->crn - #define OPCODE_1 inst_cream->opcode_1 - #define OPCODE_2 inst_cream->opcode_2 - #define CRm inst_cream->crm - #define RD cpu->Reg[inst_cream->Rd] - #define RD2 cpu->Reg[inst_cream->Rd + 1] - #define RN cpu->Reg[inst_cream->Rn] - #define RM cpu->Reg[inst_cream->Rm] - #define RS cpu->Reg[inst_cream->Rs] - #define RDHI cpu->Reg[inst_cream->RdHi] - #define RDLO cpu->Reg[inst_cream->RdLo] - #define LINK_RTN_ADDR (cpu->Reg[14] = cpu->Reg[15] + 4) - #define SET_PC (cpu->Reg[15] = cpu->Reg[15] + 8 + inst_cream->signed_immed_24) - #define SHIFTER_OPERAND inst_cream->shtop_func(cpu, inst_cream->shifter_operand) - - #define FETCH_INST if (inst_base->br != TransExtData::NON_BRANCH) goto DISPATCH; \ - inst_base = (arm_inst *)&trans_cache_buf[ptr] - - #define INC_PC(l) ptr += sizeof(arm_inst) + l - #define INC_PC_STUB ptr += sizeof(arm_inst) - -#define GDB_BP_CHECK \ - cpu->Cpsr &= ~(1 << 5); \ - cpu->Cpsr |= cpu->TFlag << 5; \ - if (GDBStub::g_server_enabled) { \ - if (GDBStub::IsMemoryBreak() || (breakpoint_data.type != GDBStub::BreakpointType::None && PC == breakpoint_data.address)) { \ - GDBStub::Break(); \ - goto END; \ - } \ +#undef RM +#undef RS + +#define CRn inst_cream->crn +#define OPCODE_1 inst_cream->opcode_1 +#define OPCODE_2 inst_cream->opcode_2 +#define CRm inst_cream->crm +#define RD cpu->Reg[inst_cream->Rd] +#define RD2 cpu->Reg[inst_cream->Rd + 1] +#define RN cpu->Reg[inst_cream->Rn] +#define RM cpu->Reg[inst_cream->Rm] +#define RS cpu->Reg[inst_cream->Rs] +#define RDHI cpu->Reg[inst_cream->RdHi] +#define RDLO cpu->Reg[inst_cream->RdLo] +#define LINK_RTN_ADDR (cpu->Reg[14] = cpu->Reg[15] + 4) +#define SET_PC (cpu->Reg[15] = cpu->Reg[15] + 8 + inst_cream->signed_immed_24) +#define SHIFTER_OPERAND inst_cream->shtop_func(cpu, inst_cream->shifter_operand) + +#define FETCH_INST \ + if (inst_base->br != TransExtData::NON_BRANCH) \ + goto DISPATCH; \ + inst_base = (arm_inst*)&trans_cache_buf[ptr] + +#define INC_PC(l) ptr += sizeof(arm_inst) + l +#define INC_PC_STUB ptr += sizeof(arm_inst) + +#define GDB_BP_CHECK \ + cpu->Cpsr &= ~(1 << 5); \ + cpu->Cpsr |= cpu->TFlag << 5; \ + if (GDBStub::g_server_enabled) { \ + if (GDBStub::IsMemoryBreak() || (breakpoint_data.type != GDBStub::BreakpointType::None && \ + PC == breakpoint_data.address)) { \ + GDBStub::Break(); \ + goto END; \ + } \ } // GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback to a // clunky switch statement. #if defined __GNUC__ || defined __clang__ -#define GOTO_NEXT_INST \ - GDB_BP_CHECK; \ - if (num_instrs >= cpu->NumInstrsToExecute) goto END; \ - num_instrs++; \ - goto *InstLabel[inst_base->idx] +#define GOTO_NEXT_INST \ + GDB_BP_CHECK; \ + if (num_instrs >= cpu->NumInstrsToExecute) \ + goto END; \ + num_instrs++; \ + goto* InstLabel[inst_base->idx] #else -#define GOTO_NEXT_INST \ - GDB_BP_CHECK; \ - if (num_instrs >= cpu->NumInstrsToExecute) goto END; \ - num_instrs++; \ - switch(inst_base->idx) { \ - case 0: goto VMLA_INST; \ - case 1: goto VMLS_INST; \ - case 2: goto VNMLA_INST; \ - case 3: goto VNMLS_INST; \ - case 4: goto VNMUL_INST; \ - case 5: goto VMUL_INST; \ - case 6: goto VADD_INST; \ - case 7: goto VSUB_INST; \ - case 8: goto VDIV_INST; \ - case 9: goto VMOVI_INST; \ - case 10: goto VMOVR_INST; \ - case 11: goto VABS_INST; \ - case 12: goto VNEG_INST; \ - case 13: goto VSQRT_INST; \ - case 14: goto VCMP_INST; \ - case 15: goto VCMP2_INST; \ - case 16: goto VCVTBDS_INST; \ - case 17: goto VCVTBFF_INST; \ - case 18: goto VCVTBFI_INST; \ - case 19: goto VMOVBRS_INST; \ - case 20: goto VMSR_INST; \ - case 21: goto VMOVBRC_INST; \ - case 22: goto VMRS_INST; \ - case 23: goto VMOVBCR_INST; \ - case 24: goto VMOVBRRSS_INST; \ - case 25: goto VMOVBRRD_INST; \ - case 26: goto VSTR_INST; \ - case 27: goto VPUSH_INST; \ - case 28: goto VSTM_INST; \ - case 29: goto VPOP_INST; \ - case 30: goto VLDR_INST; \ - case 31: goto VLDM_INST ; \ - case 32: goto SRS_INST; \ - case 33: goto RFE_INST; \ - case 34: goto BKPT_INST; \ - case 35: goto BLX_INST; \ - case 36: goto CPS_INST; \ - case 37: goto PLD_INST; \ - case 38: goto SETEND_INST; \ - case 39: goto CLREX_INST; \ - case 40: goto REV16_INST; \ - case 41: goto USAD8_INST; \ - case 42: goto SXTB_INST; \ - case 43: goto UXTB_INST; \ - case 44: goto SXTH_INST; \ - case 45: goto SXTB16_INST; \ - case 46: goto UXTH_INST; \ - case 47: goto UXTB16_INST; \ - case 48: goto CPY_INST; \ - case 49: goto UXTAB_INST; \ - case 50: goto SSUB8_INST; \ - case 51: goto SHSUB8_INST; \ - case 52: goto SSUBADDX_INST; \ - case 53: goto STREX_INST; \ - case 54: goto STREXB_INST; \ - case 55: goto SWP_INST; \ - case 56: goto SWPB_INST; \ - case 57: goto SSUB16_INST; \ - case 58: goto SSAT16_INST; \ - case 59: goto SHSUBADDX_INST; \ - case 60: goto QSUBADDX_INST; \ - case 61: goto SHADDSUBX_INST; \ - case 62: goto SHADD8_INST; \ - case 63: goto SHADD16_INST; \ - case 64: goto SEL_INST; \ - case 65: goto SADDSUBX_INST; \ - case 66: goto SADD8_INST; \ - case 67: goto SADD16_INST; \ - case 68: goto SHSUB16_INST; \ - case 69: goto UMAAL_INST; \ - case 70: goto UXTAB16_INST; \ - case 71: goto USUBADDX_INST; \ - case 72: goto USUB8_INST; \ - case 73: goto USUB16_INST; \ - case 74: goto USAT16_INST; \ - case 75: goto USADA8_INST; \ - case 76: goto UQSUBADDX_INST; \ - case 77: goto UQSUB8_INST; \ - case 78: goto UQSUB16_INST; \ - case 79: goto UQADDSUBX_INST; \ - case 80: goto UQADD8_INST; \ - case 81: goto UQADD16_INST; \ - case 82: goto SXTAB_INST; \ - case 83: goto UHSUBADDX_INST; \ - case 84: goto UHSUB8_INST; \ - case 85: goto UHSUB16_INST; \ - case 86: goto UHADDSUBX_INST; \ - case 87: goto UHADD8_INST; \ - case 88: goto UHADD16_INST; \ - case 89: goto UADDSUBX_INST; \ - case 90: goto UADD8_INST; \ - case 91: goto UADD16_INST; \ - case 92: goto SXTAH_INST; \ - case 93: goto SXTAB16_INST; \ - case 94: goto QADD8_INST; \ - case 95: goto BXJ_INST; \ - case 96: goto CLZ_INST; \ - case 97: goto UXTAH_INST; \ - case 98: goto BX_INST; \ - case 99: goto REV_INST; \ - case 100: goto BLX_INST; \ - case 101: goto REVSH_INST; \ - case 102: goto QADD_INST; \ - case 103: goto QADD16_INST; \ - case 104: goto QADDSUBX_INST; \ - case 105: goto LDREX_INST; \ - case 106: goto QDADD_INST; \ - case 107: goto QDSUB_INST; \ - case 108: goto QSUB_INST; \ - case 109: goto LDREXB_INST; \ - case 110: goto QSUB8_INST; \ - case 111: goto QSUB16_INST; \ - case 112: goto SMUAD_INST; \ - case 113: goto SMMUL_INST; \ - case 114: goto SMUSD_INST; \ - case 115: goto SMLSD_INST; \ - case 116: goto SMLSLD_INST; \ - case 117: goto SMMLA_INST; \ - case 118: goto SMMLS_INST; \ - case 119: goto SMLALD_INST; \ - case 120: goto SMLAD_INST; \ - case 121: goto SMLAW_INST; \ - case 122: goto SMULW_INST; \ - case 123: goto PKHTB_INST; \ - case 124: goto PKHBT_INST; \ - case 125: goto SMUL_INST; \ - case 126: goto SMLALXY_INST; \ - case 127: goto SMLA_INST; \ - case 128: goto MCRR_INST; \ - case 129: goto MRRC_INST; \ - case 130: goto CMP_INST; \ - case 131: goto TST_INST; \ - case 132: goto TEQ_INST; \ - case 133: goto CMN_INST; \ - case 134: goto SMULL_INST; \ - case 135: goto UMULL_INST; \ - case 136: goto UMLAL_INST; \ - case 137: goto SMLAL_INST; \ - case 138: goto MUL_INST; \ - case 139: goto MLA_INST; \ - case 140: goto SSAT_INST; \ - case 141: goto USAT_INST; \ - case 142: goto MRS_INST; \ - case 143: goto MSR_INST; \ - case 144: goto AND_INST; \ - case 145: goto BIC_INST; \ - case 146: goto LDM_INST; \ - case 147: goto EOR_INST; \ - case 148: goto ADD_INST; \ - case 149: goto RSB_INST; \ - case 150: goto RSC_INST; \ - case 151: goto SBC_INST; \ - case 152: goto ADC_INST; \ - case 153: goto SUB_INST; \ - case 154: goto ORR_INST; \ - case 155: goto MVN_INST; \ - case 156: goto MOV_INST; \ - case 157: goto STM_INST; \ - case 158: goto LDM_INST; \ - case 159: goto LDRSH_INST; \ - case 160: goto STM_INST; \ - case 161: goto LDM_INST; \ - case 162: goto LDRSB_INST; \ - case 163: goto STRD_INST; \ - case 164: goto LDRH_INST; \ - case 165: goto STRH_INST; \ - case 166: goto LDRD_INST; \ - case 167: goto STRT_INST; \ - case 168: goto STRBT_INST; \ - case 169: goto LDRBT_INST; \ - case 170: goto LDRT_INST; \ - case 171: goto MRC_INST; \ - case 172: goto MCR_INST; \ - case 173: goto MSR_INST; \ - case 174: goto MSR_INST; \ - case 175: goto MSR_INST; \ - case 176: goto MSR_INST; \ - case 177: goto MSR_INST; \ - case 178: goto LDRB_INST; \ - case 179: goto STRB_INST; \ - case 180: goto LDR_INST; \ - case 181: goto LDRCOND_INST ; \ - case 182: goto STR_INST; \ - case 183: goto CDP_INST; \ - case 184: goto STC_INST; \ - case 185: goto LDC_INST; \ - case 186: goto LDREXD_INST; \ - case 187: goto STREXD_INST; \ - case 188: goto LDREXH_INST; \ - case 189: goto STREXH_INST; \ - case 190: goto NOP_INST; \ - case 191: goto YIELD_INST; \ - case 192: goto WFE_INST; \ - case 193: goto WFI_INST; \ - case 194: goto SEV_INST; \ - case 195: goto SWI_INST; \ - case 196: goto BBL_INST; \ - case 197: goto B_2_THUMB ; \ - case 198: goto B_COND_THUMB ; \ - case 199: goto BL_1_THUMB ; \ - case 200: goto BL_2_THUMB ; \ - case 201: goto BLX_1_THUMB ; \ - case 202: goto DISPATCH; \ - case 203: goto INIT_INST_LENGTH; \ - case 204: goto END; \ +#define GOTO_NEXT_INST \ + GDB_BP_CHECK; \ + if (num_instrs >= cpu->NumInstrsToExecute) \ + goto END; \ + num_instrs++; \ + switch (inst_base->idx) { \ + case 0: \ + goto VMLA_INST; \ + case 1: \ + goto VMLS_INST; \ + case 2: \ + goto VNMLA_INST; \ + case 3: \ + goto VNMLS_INST; \ + case 4: \ + goto VNMUL_INST; \ + case 5: \ + goto VMUL_INST; \ + case 6: \ + goto VADD_INST; \ + case 7: \ + goto VSUB_INST; \ + case 8: \ + goto VDIV_INST; \ + case 9: \ + goto VMOVI_INST; \ + case 10: \ + goto VMOVR_INST; \ + case 11: \ + goto VABS_INST; \ + case 12: \ + goto VNEG_INST; \ + case 13: \ + goto VSQRT_INST; \ + case 14: \ + goto VCMP_INST; \ + case 15: \ + goto VCMP2_INST; \ + case 16: \ + goto VCVTBDS_INST; \ + case 17: \ + goto VCVTBFF_INST; \ + case 18: \ + goto VCVTBFI_INST; \ + case 19: \ + goto VMOVBRS_INST; \ + case 20: \ + goto VMSR_INST; \ + case 21: \ + goto VMOVBRC_INST; \ + case 22: \ + goto VMRS_INST; \ + case 23: \ + goto VMOVBCR_INST; \ + case 24: \ + goto VMOVBRRSS_INST; \ + case 25: \ + goto VMOVBRRD_INST; \ + case 26: \ + goto VSTR_INST; \ + case 27: \ + goto VPUSH_INST; \ + case 28: \ + goto VSTM_INST; \ + case 29: \ + goto VPOP_INST; \ + case 30: \ + goto VLDR_INST; \ + case 31: \ + goto VLDM_INST; \ + case 32: \ + goto SRS_INST; \ + case 33: \ + goto RFE_INST; \ + case 34: \ + goto BKPT_INST; \ + case 35: \ + goto BLX_INST; \ + case 36: \ + goto CPS_INST; \ + case 37: \ + goto PLD_INST; \ + case 38: \ + goto SETEND_INST; \ + case 39: \ + goto CLREX_INST; \ + case 40: \ + goto REV16_INST; \ + case 41: \ + goto USAD8_INST; \ + case 42: \ + goto SXTB_INST; \ + case 43: \ + goto UXTB_INST; \ + case 44: \ + goto SXTH_INST; \ + case 45: \ + goto SXTB16_INST; \ + case 46: \ + goto UXTH_INST; \ + case 47: \ + goto UXTB16_INST; \ + case 48: \ + goto CPY_INST; \ + case 49: \ + goto UXTAB_INST; \ + case 50: \ + goto SSUB8_INST; \ + case 51: \ + goto SHSUB8_INST; \ + case 52: \ + goto SSUBADDX_INST; \ + case 53: \ + goto STREX_INST; \ + case 54: \ + goto STREXB_INST; \ + case 55: \ + goto SWP_INST; \ + case 56: \ + goto SWPB_INST; \ + case 57: \ + goto SSUB16_INST; \ + case 58: \ + goto SSAT16_INST; \ + case 59: \ + goto SHSUBADDX_INST; \ + case 60: \ + goto QSUBADDX_INST; \ + case 61: \ + goto SHADDSUBX_INST; \ + case 62: \ + goto SHADD8_INST; \ + case 63: \ + goto SHADD16_INST; \ + case 64: \ + goto SEL_INST; \ + case 65: \ + goto SADDSUBX_INST; \ + case 66: \ + goto SADD8_INST; \ + case 67: \ + goto SADD16_INST; \ + case 68: \ + goto SHSUB16_INST; \ + case 69: \ + goto UMAAL_INST; \ + case 70: \ + goto UXTAB16_INST; \ + case 71: \ + goto USUBADDX_INST; \ + case 72: \ + goto USUB8_INST; \ + case 73: \ + goto USUB16_INST; \ + case 74: \ + goto USAT16_INST; \ + case 75: \ + goto USADA8_INST; \ + case 76: \ + goto UQSUBADDX_INST; \ + case 77: \ + goto UQSUB8_INST; \ + case 78: \ + goto UQSUB16_INST; \ + case 79: \ + goto UQADDSUBX_INST; \ + case 80: \ + goto UQADD8_INST; \ + case 81: \ + goto UQADD16_INST; \ + case 82: \ + goto SXTAB_INST; \ + case 83: \ + goto UHSUBADDX_INST; \ + case 84: \ + goto UHSUB8_INST; \ + case 85: \ + goto UHSUB16_INST; \ + case 86: \ + goto UHADDSUBX_INST; \ + case 87: \ + goto UHADD8_INST; \ + case 88: \ + goto UHADD16_INST; \ + case 89: \ + goto UADDSUBX_INST; \ + case 90: \ + goto UADD8_INST; \ + case 91: \ + goto UADD16_INST; \ + case 92: \ + goto SXTAH_INST; \ + case 93: \ + goto SXTAB16_INST; \ + case 94: \ + goto QADD8_INST; \ + case 95: \ + goto BXJ_INST; \ + case 96: \ + goto CLZ_INST; \ + case 97: \ + goto UXTAH_INST; \ + case 98: \ + goto BX_INST; \ + case 99: \ + goto REV_INST; \ + case 100: \ + goto BLX_INST; \ + case 101: \ + goto REVSH_INST; \ + case 102: \ + goto QADD_INST; \ + case 103: \ + goto QADD16_INST; \ + case 104: \ + goto QADDSUBX_INST; \ + case 105: \ + goto LDREX_INST; \ + case 106: \ + goto QDADD_INST; \ + case 107: \ + goto QDSUB_INST; \ + case 108: \ + goto QSUB_INST; \ + case 109: \ + goto LDREXB_INST; \ + case 110: \ + goto QSUB8_INST; \ + case 111: \ + goto QSUB16_INST; \ + case 112: \ + goto SMUAD_INST; \ + case 113: \ + goto SMMUL_INST; \ + case 114: \ + goto SMUSD_INST; \ + case 115: \ + goto SMLSD_INST; \ + case 116: \ + goto SMLSLD_INST; \ + case 117: \ + goto SMMLA_INST; \ + case 118: \ + goto SMMLS_INST; \ + case 119: \ + goto SMLALD_INST; \ + case 120: \ + goto SMLAD_INST; \ + case 121: \ + goto SMLAW_INST; \ + case 122: \ + goto SMULW_INST; \ + case 123: \ + goto PKHTB_INST; \ + case 124: \ + goto PKHBT_INST; \ + case 125: \ + goto SMUL_INST; \ + case 126: \ + goto SMLALXY_INST; \ + case 127: \ + goto SMLA_INST; \ + case 128: \ + goto MCRR_INST; \ + case 129: \ + goto MRRC_INST; \ + case 130: \ + goto CMP_INST; \ + case 131: \ + goto TST_INST; \ + case 132: \ + goto TEQ_INST; \ + case 133: \ + goto CMN_INST; \ + case 134: \ + goto SMULL_INST; \ + case 135: \ + goto UMULL_INST; \ + case 136: \ + goto UMLAL_INST; \ + case 137: \ + goto SMLAL_INST; \ + case 138: \ + goto MUL_INST; \ + case 139: \ + goto MLA_INST; \ + case 140: \ + goto SSAT_INST; \ + case 141: \ + goto USAT_INST; \ + case 142: \ + goto MRS_INST; \ + case 143: \ + goto MSR_INST; \ + case 144: \ + goto AND_INST; \ + case 145: \ + goto BIC_INST; \ + case 146: \ + goto LDM_INST; \ + case 147: \ + goto EOR_INST; \ + case 148: \ + goto ADD_INST; \ + case 149: \ + goto RSB_INST; \ + case 150: \ + goto RSC_INST; \ + case 151: \ + goto SBC_INST; \ + case 152: \ + goto ADC_INST; \ + case 153: \ + goto SUB_INST; \ + case 154: \ + goto ORR_INST; \ + case 155: \ + goto MVN_INST; \ + case 156: \ + goto MOV_INST; \ + case 157: \ + goto STM_INST; \ + case 158: \ + goto LDM_INST; \ + case 159: \ + goto LDRSH_INST; \ + case 160: \ + goto STM_INST; \ + case 161: \ + goto LDM_INST; \ + case 162: \ + goto LDRSB_INST; \ + case 163: \ + goto STRD_INST; \ + case 164: \ + goto LDRH_INST; \ + case 165: \ + goto STRH_INST; \ + case 166: \ + goto LDRD_INST; \ + case 167: \ + goto STRT_INST; \ + case 168: \ + goto STRBT_INST; \ + case 169: \ + goto LDRBT_INST; \ + case 170: \ + goto LDRT_INST; \ + case 171: \ + goto MRC_INST; \ + case 172: \ + goto MCR_INST; \ + case 173: \ + goto MSR_INST; \ + case 174: \ + goto MSR_INST; \ + case 175: \ + goto MSR_INST; \ + case 176: \ + goto MSR_INST; \ + case 177: \ + goto MSR_INST; \ + case 178: \ + goto LDRB_INST; \ + case 179: \ + goto STRB_INST; \ + case 180: \ + goto LDR_INST; \ + case 181: \ + goto LDRCOND_INST; \ + case 182: \ + goto STR_INST; \ + case 183: \ + goto CDP_INST; \ + case 184: \ + goto STC_INST; \ + case 185: \ + goto LDC_INST; \ + case 186: \ + goto LDREXD_INST; \ + case 187: \ + goto STREXD_INST; \ + case 188: \ + goto LDREXH_INST; \ + case 189: \ + goto STREXH_INST; \ + case 190: \ + goto NOP_INST; \ + case 191: \ + goto YIELD_INST; \ + case 192: \ + goto WFE_INST; \ + case 193: \ + goto WFI_INST; \ + case 194: \ + goto SEV_INST; \ + case 195: \ + goto SWI_INST; \ + case 196: \ + goto BBL_INST; \ + case 197: \ + goto B_2_THUMB; \ + case 198: \ + goto B_COND_THUMB; \ + case 199: \ + goto BL_1_THUMB; \ + case 200: \ + goto BL_2_THUMB; \ + case 201: \ + goto BLX_1_THUMB; \ + case 202: \ + goto DISPATCH; \ + case 203: \ + goto INIT_INST_LENGTH; \ + case 204: \ + goto END; \ } #endif - #define UPDATE_NFLAG(dst) (cpu->NFlag = BIT(dst, 31) ? 1 : 0) - #define UPDATE_ZFLAG(dst) (cpu->ZFlag = dst ? 0 : 1) - #define UPDATE_CFLAG_WITH_SC (cpu->CFlag = cpu->shifter_carry_out) - - #define SAVE_NZCVT cpu->Cpsr = (cpu->Cpsr & 0x0fffffdf) | \ - (cpu->NFlag << 31) | \ - (cpu->ZFlag << 30) | \ - (cpu->CFlag << 29) | \ - (cpu->VFlag << 28) | \ - (cpu->TFlag << 5) - #define LOAD_NZCVT cpu->NFlag = (cpu->Cpsr >> 31); \ - cpu->ZFlag = (cpu->Cpsr >> 30) & 1; \ - cpu->CFlag = (cpu->Cpsr >> 29) & 1; \ - cpu->VFlag = (cpu->Cpsr >> 28) & 1; \ - cpu->TFlag = (cpu->Cpsr >> 5) & 1; - - #define CurrentModeHasSPSR (cpu->Mode != SYSTEM32MODE) && (cpu->Mode != USER32MODE) - #define PC (cpu->Reg[15]) - - // GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback - // to a clunky switch statement. +#define UPDATE_NFLAG(dst) (cpu->NFlag = BIT(dst, 31) ? 1 : 0) +#define UPDATE_ZFLAG(dst) (cpu->ZFlag = dst ? 0 : 1) +#define UPDATE_CFLAG_WITH_SC (cpu->CFlag = cpu->shifter_carry_out) + +#define SAVE_NZCVT \ + cpu->Cpsr = (cpu->Cpsr & 0x0fffffdf) | (cpu->NFlag << 31) | (cpu->ZFlag << 30) | \ + (cpu->CFlag << 29) | (cpu->VFlag << 28) | (cpu->TFlag << 5) +#define LOAD_NZCVT \ + cpu->NFlag = (cpu->Cpsr >> 31); \ + cpu->ZFlag = (cpu->Cpsr >> 30) & 1; \ + cpu->CFlag = (cpu->Cpsr >> 29) & 1; \ + cpu->VFlag = (cpu->Cpsr >> 28) & 1; \ + cpu->TFlag = (cpu->Cpsr >> 5) & 1; + +#define CurrentModeHasSPSR (cpu->Mode != SYSTEM32MODE) && (cpu->Mode != USER32MODE) +#define PC (cpu->Reg[15]) + +// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback +// to a clunky switch statement. #if defined __GNUC__ || defined __clang__ - void *InstLabel[] = { - &&VMLA_INST, &&VMLS_INST, &&VNMLA_INST, &&VNMLS_INST, &&VNMUL_INST, &&VMUL_INST, &&VADD_INST, &&VSUB_INST, - &&VDIV_INST, &&VMOVI_INST, &&VMOVR_INST, &&VABS_INST, &&VNEG_INST, &&VSQRT_INST, &&VCMP_INST, &&VCMP2_INST, &&VCVTBDS_INST, - &&VCVTBFF_INST, &&VCVTBFI_INST, &&VMOVBRS_INST, &&VMSR_INST, &&VMOVBRC_INST, &&VMRS_INST, &&VMOVBCR_INST, &&VMOVBRRSS_INST, - &&VMOVBRRD_INST, &&VSTR_INST, &&VPUSH_INST, &&VSTM_INST, &&VPOP_INST, &&VLDR_INST, &&VLDM_INST, - - &&SRS_INST,&&RFE_INST,&&BKPT_INST,&&BLX_INST,&&CPS_INST,&&PLD_INST,&&SETEND_INST,&&CLREX_INST,&&REV16_INST,&&USAD8_INST,&&SXTB_INST, - &&UXTB_INST,&&SXTH_INST,&&SXTB16_INST,&&UXTH_INST,&&UXTB16_INST,&&CPY_INST,&&UXTAB_INST,&&SSUB8_INST,&&SHSUB8_INST,&&SSUBADDX_INST, - &&STREX_INST,&&STREXB_INST,&&SWP_INST,&&SWPB_INST,&&SSUB16_INST,&&SSAT16_INST,&&SHSUBADDX_INST,&&QSUBADDX_INST,&&SHADDSUBX_INST, - &&SHADD8_INST,&&SHADD16_INST,&&SEL_INST,&&SADDSUBX_INST,&&SADD8_INST,&&SADD16_INST,&&SHSUB16_INST,&&UMAAL_INST,&&UXTAB16_INST, - &&USUBADDX_INST,&&USUB8_INST,&&USUB16_INST,&&USAT16_INST,&&USADA8_INST,&&UQSUBADDX_INST,&&UQSUB8_INST,&&UQSUB16_INST, - &&UQADDSUBX_INST,&&UQADD8_INST,&&UQADD16_INST,&&SXTAB_INST,&&UHSUBADDX_INST,&&UHSUB8_INST,&&UHSUB16_INST,&&UHADDSUBX_INST,&&UHADD8_INST, - &&UHADD16_INST,&&UADDSUBX_INST,&&UADD8_INST,&&UADD16_INST,&&SXTAH_INST,&&SXTAB16_INST,&&QADD8_INST,&&BXJ_INST,&&CLZ_INST,&&UXTAH_INST, - &&BX_INST,&&REV_INST,&&BLX_INST,&&REVSH_INST,&&QADD_INST,&&QADD16_INST,&&QADDSUBX_INST,&&LDREX_INST,&&QDADD_INST,&&QDSUB_INST, - &&QSUB_INST,&&LDREXB_INST,&&QSUB8_INST,&&QSUB16_INST,&&SMUAD_INST,&&SMMUL_INST,&&SMUSD_INST,&&SMLSD_INST,&&SMLSLD_INST,&&SMMLA_INST, - &&SMMLS_INST,&&SMLALD_INST,&&SMLAD_INST,&&SMLAW_INST,&&SMULW_INST,&&PKHTB_INST,&&PKHBT_INST,&&SMUL_INST,&&SMLALXY_INST,&&SMLA_INST, - &&MCRR_INST,&&MRRC_INST,&&CMP_INST,&&TST_INST,&&TEQ_INST,&&CMN_INST,&&SMULL_INST,&&UMULL_INST,&&UMLAL_INST,&&SMLAL_INST,&&MUL_INST, - &&MLA_INST,&&SSAT_INST,&&USAT_INST,&&MRS_INST,&&MSR_INST,&&AND_INST,&&BIC_INST,&&LDM_INST,&&EOR_INST,&&ADD_INST,&&RSB_INST,&&RSC_INST, - &&SBC_INST,&&ADC_INST,&&SUB_INST,&&ORR_INST,&&MVN_INST,&&MOV_INST,&&STM_INST,&&LDM_INST,&&LDRSH_INST,&&STM_INST,&&LDM_INST,&&LDRSB_INST, - &&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST, - &&MSR_INST, &&MSR_INST, &&MSR_INST, &&MSR_INST, &&MSR_INST, - &&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST, &&LDREXD_INST, - &&STREXD_INST,&&LDREXH_INST,&&STREXH_INST, &&NOP_INST, &&YIELD_INST, &&WFE_INST, &&WFI_INST, &&SEV_INST, &&SWI_INST,&&BBL_INST, - &&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH, - &&INIT_INST_LENGTH,&&END - }; + void* InstLabel[] = {&&VMLA_INST, + &&VMLS_INST, + &&VNMLA_INST, + &&VNMLS_INST, + &&VNMUL_INST, + &&VMUL_INST, + &&VADD_INST, + &&VSUB_INST, + &&VDIV_INST, + &&VMOVI_INST, + &&VMOVR_INST, + &&VABS_INST, + &&VNEG_INST, + &&VSQRT_INST, + &&VCMP_INST, + &&VCMP2_INST, + &&VCVTBDS_INST, + &&VCVTBFF_INST, + &&VCVTBFI_INST, + &&VMOVBRS_INST, + &&VMSR_INST, + &&VMOVBRC_INST, + &&VMRS_INST, + &&VMOVBCR_INST, + &&VMOVBRRSS_INST, + &&VMOVBRRD_INST, + &&VSTR_INST, + &&VPUSH_INST, + &&VSTM_INST, + &&VPOP_INST, + &&VLDR_INST, + &&VLDM_INST, + + &&SRS_INST, + &&RFE_INST, + &&BKPT_INST, + &&BLX_INST, + &&CPS_INST, + &&PLD_INST, + &&SETEND_INST, + &&CLREX_INST, + &&REV16_INST, + &&USAD8_INST, + &&SXTB_INST, + &&UXTB_INST, + &&SXTH_INST, + &&SXTB16_INST, + &&UXTH_INST, + &&UXTB16_INST, + &&CPY_INST, + &&UXTAB_INST, + &&SSUB8_INST, + &&SHSUB8_INST, + &&SSUBADDX_INST, + &&STREX_INST, + &&STREXB_INST, + &&SWP_INST, + &&SWPB_INST, + &&SSUB16_INST, + &&SSAT16_INST, + &&SHSUBADDX_INST, + &&QSUBADDX_INST, + &&SHADDSUBX_INST, + &&SHADD8_INST, + &&SHADD16_INST, + &&SEL_INST, + &&SADDSUBX_INST, + &&SADD8_INST, + &&SADD16_INST, + &&SHSUB16_INST, + &&UMAAL_INST, + &&UXTAB16_INST, + &&USUBADDX_INST, + &&USUB8_INST, + &&USUB16_INST, + &&USAT16_INST, + &&USADA8_INST, + &&UQSUBADDX_INST, + &&UQSUB8_INST, + &&UQSUB16_INST, + &&UQADDSUBX_INST, + &&UQADD8_INST, + &&UQADD16_INST, + &&SXTAB_INST, + &&UHSUBADDX_INST, + &&UHSUB8_INST, + &&UHSUB16_INST, + &&UHADDSUBX_INST, + &&UHADD8_INST, + &&UHADD16_INST, + &&UADDSUBX_INST, + &&UADD8_INST, + &&UADD16_INST, + &&SXTAH_INST, + &&SXTAB16_INST, + &&QADD8_INST, + &&BXJ_INST, + &&CLZ_INST, + &&UXTAH_INST, + &&BX_INST, + &&REV_INST, + &&BLX_INST, + &&REVSH_INST, + &&QADD_INST, + &&QADD16_INST, + &&QADDSUBX_INST, + &&LDREX_INST, + &&QDADD_INST, + &&QDSUB_INST, + &&QSUB_INST, + &&LDREXB_INST, + &&QSUB8_INST, + &&QSUB16_INST, + &&SMUAD_INST, + &&SMMUL_INST, + &&SMUSD_INST, + &&SMLSD_INST, + &&SMLSLD_INST, + &&SMMLA_INST, + &&SMMLS_INST, + &&SMLALD_INST, + &&SMLAD_INST, + &&SMLAW_INST, + &&SMULW_INST, + &&PKHTB_INST, + &&PKHBT_INST, + &&SMUL_INST, + &&SMLALXY_INST, + &&SMLA_INST, + &&MCRR_INST, + &&MRRC_INST, + &&CMP_INST, + &&TST_INST, + &&TEQ_INST, + &&CMN_INST, + &&SMULL_INST, + &&UMULL_INST, + &&UMLAL_INST, + &&SMLAL_INST, + &&MUL_INST, + &&MLA_INST, + &&SSAT_INST, + &&USAT_INST, + &&MRS_INST, + &&MSR_INST, + &&AND_INST, + &&BIC_INST, + &&LDM_INST, + &&EOR_INST, + &&ADD_INST, + &&RSB_INST, + &&RSC_INST, + &&SBC_INST, + &&ADC_INST, + &&SUB_INST, + &&ORR_INST, + &&MVN_INST, + &&MOV_INST, + &&STM_INST, + &&LDM_INST, + &&LDRSH_INST, + &&STM_INST, + &&LDM_INST, + &&LDRSB_INST, + &&STRD_INST, + &&LDRH_INST, + &&STRH_INST, + &&LDRD_INST, + &&STRT_INST, + &&STRBT_INST, + &&LDRBT_INST, + &&LDRT_INST, + &&MRC_INST, + &&MCR_INST, + &&MSR_INST, + &&MSR_INST, + &&MSR_INST, + &&MSR_INST, + &&MSR_INST, + &&LDRB_INST, + &&STRB_INST, + &&LDR_INST, + &&LDRCOND_INST, + &&STR_INST, + &&CDP_INST, + &&STC_INST, + &&LDC_INST, + &&LDREXD_INST, + &&STREXD_INST, + &&LDREXH_INST, + &&STREXH_INST, + &&NOP_INST, + &&YIELD_INST, + &&WFE_INST, + &&WFI_INST, + &&SEV_INST, + &&SWI_INST, + &&BBL_INST, + &&B_2_THUMB, + &&B_COND_THUMB, + &&BL_1_THUMB, + &&BL_2_THUMB, + &&BLX_1_THUMB, + &&DISPATCH, + &&INIT_INST_LENGTH, + &&END}; #endif arm_inst* inst_base; unsigned int addr; @@ -1204,516 +1627,517 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { int ptr; LOAD_NZCVT; - DISPATCH: - { - if (!cpu->NirqSig) { - if (!(cpu->Cpsr & 0x80)) { - goto END; - } +DISPATCH : { + if (!cpu->NirqSig) { + if (!(cpu->Cpsr & 0x80)) { + goto END; } + } - if (cpu->TFlag) - cpu->Reg[15] &= 0xfffffffe; - else - cpu->Reg[15] &= 0xfffffffc; - - // Find the cached instruction cream, otherwise translate it... - auto itr = cpu->instruction_cache.find(cpu->Reg[15]); - if (itr != cpu->instruction_cache.end()) { - ptr = itr->second; - } else if (cpu->NumInstrsToExecute != 1) { - if (InterpreterTranslateBlock(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION) - goto END; - } else { - if (InterpreterTranslateSingle(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION) - goto END; - } + if (cpu->TFlag) + cpu->Reg[15] &= 0xfffffffe; + else + cpu->Reg[15] &= 0xfffffffc; + + // Find the cached instruction cream, otherwise translate it... + auto itr = cpu->instruction_cache.find(cpu->Reg[15]); + if (itr != cpu->instruction_cache.end()) { + ptr = itr->second; + } else if (cpu->NumInstrsToExecute != 1) { + if (InterpreterTranslateBlock(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION) + goto END; + } else { + if (InterpreterTranslateSingle(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION) + goto END; + } - // Find breakpoint if one exists within the block - if (GDBStub::g_server_enabled && GDBStub::IsConnected()) { - breakpoint_data = GDBStub::GetNextBreakpointFromAddress(cpu->Reg[15], GDBStub::BreakpointType::Execute); - } + // Find breakpoint if one exists within the block + if (GDBStub::g_server_enabled && GDBStub::IsConnected()) { + breakpoint_data = + GDBStub::GetNextBreakpointFromAddress(cpu->Reg[15], GDBStub::BreakpointType::Execute); + } - inst_base = (arm_inst *)&trans_cache_buf[ptr]; - GOTO_NEXT_INST; + inst_base = (arm_inst*)&trans_cache_buf[ptr]; + GOTO_NEXT_INST; +} +ADC_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + adc_inst* const inst_cream = (adc_inst*)inst_base->component; + + u32 rn_val = RN; + if (inst_cream->Rn == 15) + rn_val += 2 * cpu->GetInstructionSize(); + + bool carry; + bool overflow; + RD = AddWithCarry(rn_val, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); + + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); + LOAD_NZCVT; + } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(adc_inst)); + goto DISPATCH; + } } - ADC_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - adc_inst* const inst_cream = (adc_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(adc_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +ADD_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + add_inst* const inst_cream = (add_inst*)inst_base->component; - u32 rn_val = RN; - if (inst_cream->Rn == 15) - rn_val += 2 * cpu->GetInstructionSize(); + u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn); - bool carry; - bool overflow; - RD = AddWithCarry(rn_val, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); + bool carry; + bool overflow; + RD = AddWithCarry(rn_val, SHIFTER_OPERAND, 0, &carry, &overflow); - if (inst_cream->S && (inst_cream->Rd == 15)) { - if (CurrentModeHasSPSR) { - cpu->Cpsr = cpu->Spsr_copy; - cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); - LOAD_NZCVT; - } - } else if (inst_cream->S) { - UPDATE_NFLAG(RD); - UPDATE_ZFLAG(RD); - cpu->CFlag = carry; - cpu->VFlag = overflow; - } - if (inst_cream->Rd == 15) { - INC_PC(sizeof(adc_inst)); - goto DISPATCH; + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F); + LOAD_NZCVT; } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(adc_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - ADD_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - add_inst* const inst_cream = (add_inst*)inst_base->component; - - u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn); - - bool carry; - bool overflow; - RD = AddWithCarry(rn_val, SHIFTER_OPERAND, 0, &carry, &overflow); - - if (inst_cream->S && (inst_cream->Rd == 15)) { - if (CurrentModeHasSPSR) { - cpu->Cpsr = cpu->Spsr_copy; - cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F); - LOAD_NZCVT; - } - } else if (inst_cream->S) { - UPDATE_NFLAG(RD); - UPDATE_ZFLAG(RD); - cpu->CFlag = carry; - cpu->VFlag = overflow; - } - if (inst_cream->Rd == 15) { - INC_PC(sizeof(add_inst)); - goto DISPATCH; - } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(add_inst)); + goto DISPATCH; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(add_inst)); - FETCH_INST; - GOTO_NEXT_INST; } - AND_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - and_inst* const inst_cream = (and_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(add_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +AND_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + and_inst* const inst_cream = (and_inst*)inst_base->component; - u32 lop = RN; - u32 rop = SHIFTER_OPERAND; + u32 lop = RN; + u32 rop = SHIFTER_OPERAND; - if (inst_cream->Rn == 15) - lop += 2 * cpu->GetInstructionSize(); + if (inst_cream->Rn == 15) + lop += 2 * cpu->GetInstructionSize(); - RD = lop & rop; + RD = lop & rop; - if (inst_cream->S && (inst_cream->Rd == 15)) { - if (CurrentModeHasSPSR) { - cpu->Cpsr = cpu->Spsr_copy; - cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F); - LOAD_NZCVT; - } - } else if (inst_cream->S) { - UPDATE_NFLAG(RD); - UPDATE_ZFLAG(RD); - UPDATE_CFLAG_WITH_SC; - } - if (inst_cream->Rd == 15) { - INC_PC(sizeof(and_inst)); - goto DISPATCH; + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F); + LOAD_NZCVT; } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + UPDATE_CFLAG_WITH_SC; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(and_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - BBL_INST: - { - if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { - bbl_inst *inst_cream = (bbl_inst *)inst_base->component; - if (inst_cream->L) { - LINK_RTN_ADDR; - } - SET_PC; - INC_PC(sizeof(bbl_inst)); + if (inst_cream->Rd == 15) { + INC_PC(sizeof(and_inst)); goto DISPATCH; } - cpu->Reg[15] += cpu->GetInstructionSize(); + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(and_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +BBL_INST : { + if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { + bbl_inst* inst_cream = (bbl_inst*)inst_base->component; + if (inst_cream->L) { + LINK_RTN_ADDR; + } + SET_PC; INC_PC(sizeof(bbl_inst)); goto DISPATCH; } - BIC_INST: - { - bic_inst *inst_cream = (bic_inst *)inst_base->component; - if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { - u32 lop = RN; - if (inst_cream->Rn == 15) { - lop += 2 * cpu->GetInstructionSize(); - } - u32 rop = SHIFTER_OPERAND; - RD = lop & (~rop); - if ((inst_cream->S) && (inst_cream->Rd == 15)) { - if (CurrentModeHasSPSR) { - cpu->Cpsr = cpu->Spsr_copy; - cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); - LOAD_NZCVT; - } - } else if (inst_cream->S) { - UPDATE_NFLAG(RD); - UPDATE_ZFLAG(RD); - UPDATE_CFLAG_WITH_SC; - } - if (inst_cream->Rd == 15) { - INC_PC(sizeof(bic_inst)); - goto DISPATCH; - } - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(bic_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - BKPT_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component; - LOG_DEBUG(Core_ARM11, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm); + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(bbl_inst)); + goto DISPATCH; +} +BIC_INST : { + bic_inst* inst_cream = (bic_inst*)inst_base->component; + if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { + u32 lop = RN; + if (inst_cream->Rn == 15) { + lop += 2 * cpu->GetInstructionSize(); } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(bkpt_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - BLX_INST: - { - blx_inst *inst_cream = (blx_inst *)inst_base->component; - if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { - unsigned int inst = inst_cream->inst; - if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) { - const u32 jump_address = cpu->Reg[inst_cream->val.Rm]; - cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize()); - if(cpu->TFlag) - cpu->Reg[14] |= 0x1; - cpu->Reg[15] = jump_address & 0xfffffffe; - cpu->TFlag = jump_address & 0x1; - } else { - cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize()); - cpu->TFlag = 0x1; - int signed_int = inst_cream->val.signed_immed_24; - signed_int = (signed_int & 0x800000) ? (0x3F000000 | signed_int) : signed_int; - signed_int = signed_int << 2; - cpu->Reg[15] = cpu->Reg[15] + 8 + signed_int + (BIT(inst, 24) << 1); + u32 rop = SHIFTER_OPERAND; + RD = lop & (~rop); + if ((inst_cream->S) && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); + LOAD_NZCVT; } - INC_PC(sizeof(blx_inst)); + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + UPDATE_CFLAG_WITH_SC; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(bic_inst)); goto DISPATCH; } - cpu->Reg[15] += cpu->GetInstructionSize(); + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(bic_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +BKPT_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component; + LOG_DEBUG(Core_ARM11, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm); + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(bkpt_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +BLX_INST : { + blx_inst* inst_cream = (blx_inst*)inst_base->component; + if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { + unsigned int inst = inst_cream->inst; + if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) { + const u32 jump_address = cpu->Reg[inst_cream->val.Rm]; + cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize()); + if (cpu->TFlag) + cpu->Reg[14] |= 0x1; + cpu->Reg[15] = jump_address & 0xfffffffe; + cpu->TFlag = jump_address & 0x1; + } else { + cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize()); + cpu->TFlag = 0x1; + int signed_int = inst_cream->val.signed_immed_24; + signed_int = (signed_int & 0x800000) ? (0x3F000000 | signed_int) : signed_int; + signed_int = signed_int << 2; + cpu->Reg[15] = cpu->Reg[15] + 8 + signed_int + (BIT(inst, 24) << 1); + } INC_PC(sizeof(blx_inst)); goto DISPATCH; } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(blx_inst)); + goto DISPATCH; +} - BX_INST: - BXJ_INST: - { - // Note that only the 'fail' case of BXJ is emulated. This is because - // the facilities for Jazelle emulation are not implemented. - // - // According to the ARM documentation on BXJ, if setting the J bit in the APSR - // fails, then BXJ functions identically like a regular BX instruction. - // - // This is sufficient for citra, as the CPU for the 3DS does not implement Jazelle. +BX_INST: +BXJ_INST : { + // Note that only the 'fail' case of BXJ is emulated. This is because + // the facilities for Jazelle emulation are not implemented. + // + // According to the ARM documentation on BXJ, if setting the J bit in the APSR + // fails, then BXJ functions identically like a regular BX instruction. + // + // This is sufficient for citra, as the CPU for the 3DS does not implement Jazelle. - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - bx_inst* const inst_cream = (bx_inst*)inst_base->component; + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + bx_inst* const inst_cream = (bx_inst*)inst_base->component; - u32 address = RM; + u32 address = RM; - if (inst_cream->Rm == 15) - address += 2 * cpu->GetInstructionSize(); + if (inst_cream->Rm == 15) + address += 2 * cpu->GetInstructionSize(); - cpu->TFlag = address & 1; - cpu->Reg[15] = address & 0xfffffffe; - INC_PC(sizeof(bx_inst)); - goto DISPATCH; - } - - cpu->Reg[15] += cpu->GetInstructionSize(); + cpu->TFlag = address & 1; + cpu->Reg[15] = address & 0xfffffffe; INC_PC(sizeof(bx_inst)); goto DISPATCH; } - CDP_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - // Undefined instruction here - cpu->NumInstrsToExecute = 0; - return num_instrs; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(bx_inst)); + goto DISPATCH; +} + +CDP_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + // Undefined instruction here + cpu->NumInstrsToExecute = 0; + return num_instrs; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(cdp_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} + +CLREX_INST : { + cpu->UnsetExclusiveMemoryAddress(); + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(clrex_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +CLZ_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + clz_inst* inst_cream = (clz_inst*)inst_base->component; + RD = clz(RM); + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(clz_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +CMN_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + cmn_inst* const inst_cream = (cmn_inst*)inst_base->component; + + u32 rn_val = RN; + if (inst_cream->Rn == 15) + rn_val += 2 * cpu->GetInstructionSize(); + + bool carry; + bool overflow; + u32 result = AddWithCarry(rn_val, SHIFTER_OPERAND, 0, &carry, &overflow); + + UPDATE_NFLAG(result); + UPDATE_ZFLAG(result); + cpu->CFlag = carry; + cpu->VFlag = overflow; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(cmn_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +CMP_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + cmp_inst* const inst_cream = (cmp_inst*)inst_base->component; + + u32 rn_val = RN; + if (inst_cream->Rn == 15) + rn_val += 2 * cpu->GetInstructionSize(); + + bool carry; + bool overflow; + u32 result = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow); + + UPDATE_NFLAG(result); + UPDATE_ZFLAG(result); + cpu->CFlag = carry; + cpu->VFlag = overflow; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(cmp_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +CPS_INST : { + cps_inst* inst_cream = (cps_inst*)inst_base->component; + u32 aif_val = 0; + u32 aif_mask = 0; + if (cpu->InAPrivilegedMode()) { + if (inst_cream->imod1) { + if (inst_cream->A) { + aif_val |= (inst_cream->imod0 << 8); + aif_mask |= 1 << 8; + } + if (inst_cream->I) { + aif_val |= (inst_cream->imod0 << 7); + aif_mask |= 1 << 7; + } + if (inst_cream->F) { + aif_val |= (inst_cream->imod0 << 6); + aif_mask |= 1 << 6; + } + aif_mask = ~aif_mask; + cpu->Cpsr = (cpu->Cpsr & aif_mask) | aif_val; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(cdp_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - - CLREX_INST: - { - cpu->UnsetExclusiveMemoryAddress(); - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(clrex_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - CLZ_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - clz_inst* inst_cream = (clz_inst*)inst_base->component; - RD = clz(RM); + if (inst_cream->mmod) { + cpu->Cpsr = (cpu->Cpsr & 0xffffffe0) | inst_cream->mode; + cpu->ChangePrivilegeMode(inst_cream->mode); } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(clz_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - CMN_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - cmn_inst* const inst_cream = (cmn_inst*)inst_base->component; - - u32 rn_val = RN; - if (inst_cream->Rn == 15) - rn_val += 2 * cpu->GetInstructionSize(); - - bool carry; - bool overflow; - u32 result = AddWithCarry(rn_val, SHIFTER_OPERAND, 0, &carry, &overflow); - - UPDATE_NFLAG(result); - UPDATE_ZFLAG(result); - cpu->CFlag = carry; - cpu->VFlag = overflow; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(cps_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +CPY_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + mov_inst* inst_cream = (mov_inst*)inst_base->component; + + RD = SHIFTER_OPERAND; + if (inst_cream->Rd == 15) { + INC_PC(sizeof(mov_inst)); + goto DISPATCH; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(cmn_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - CMP_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - cmp_inst* const inst_cream = (cmp_inst*)inst_base->component; - - u32 rn_val = RN; - if (inst_cream->Rn == 15) - rn_val += 2 * cpu->GetInstructionSize(); - - bool carry; - bool overflow; - u32 result = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow); - - UPDATE_NFLAG(result); - UPDATE_ZFLAG(result); - cpu->CFlag = carry; - cpu->VFlag = overflow; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(mov_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +EOR_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + eor_inst* inst_cream = (eor_inst*)inst_base->component; + + u32 lop = RN; + if (inst_cream->Rn == 15) { + lop += 2 * cpu->GetInstructionSize(); } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(cmp_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - CPS_INST: - { - cps_inst *inst_cream = (cps_inst *)inst_base->component; - u32 aif_val = 0; - u32 aif_mask = 0; - if (cpu->InAPrivilegedMode()) { - if (inst_cream->imod1) { - if (inst_cream->A) { - aif_val |= (inst_cream->imod0 << 8); - aif_mask |= 1 << 8; - } - if (inst_cream->I) { - aif_val |= (inst_cream->imod0 << 7); - aif_mask |= 1 << 7; - } - if (inst_cream->F) { - aif_val |= (inst_cream->imod0 << 6); - aif_mask |= 1 << 6; - } - aif_mask = ~aif_mask; - cpu->Cpsr = (cpu->Cpsr & aif_mask) | aif_val; - } - if (inst_cream->mmod) { - cpu->Cpsr = (cpu->Cpsr & 0xffffffe0) | inst_cream->mode; - cpu->ChangePrivilegeMode(inst_cream->mode); + u32 rop = SHIFTER_OPERAND; + RD = lop ^ rop; + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); + LOAD_NZCVT; } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + UPDATE_CFLAG_WITH_SC; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(eor_inst)); + goto DISPATCH; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(cps_inst)); - FETCH_INST; - GOTO_NEXT_INST; } - CPY_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - mov_inst* inst_cream = (mov_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(eor_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +LDC_INST : { + // Instruction not implemented + // LOG_CRITICAL(Core_ARM11, "unimplemented instruction"); + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldc_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +LDM_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr); - RD = SHIFTER_OPERAND; - if (inst_cream->Rd == 15) { - INC_PC(sizeof(mov_inst)); - goto DISPATCH; - } - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(mov_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - EOR_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - eor_inst* inst_cream = (eor_inst*)inst_base->component; - - u32 lop = RN; - if (inst_cream->Rn == 15) { - lop += 2 * cpu->GetInstructionSize(); - } - u32 rop = SHIFTER_OPERAND; - RD = lop ^ rop; - if (inst_cream->S && (inst_cream->Rd == 15)) { - if (CurrentModeHasSPSR) { - cpu->Cpsr = cpu->Spsr_copy; - cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); - LOAD_NZCVT; + unsigned int inst = inst_cream->inst; + if (BIT(inst, 22) && !BIT(inst, 15)) { + for (int i = 0; i < 13; i++) { + if (BIT(inst, i)) { + cpu->Reg[i] = cpu->ReadMemory32(addr); + addr += 4; } - } else if (inst_cream->S) { - UPDATE_NFLAG(RD); - UPDATE_ZFLAG(RD); - UPDATE_CFLAG_WITH_SC; } - if (inst_cream->Rd == 15) { - INC_PC(sizeof(eor_inst)); - goto DISPATCH; + if (BIT(inst, 13)) { + if (cpu->Mode == USER32MODE) + cpu->Reg[13] = cpu->ReadMemory32(addr); + else + cpu->Reg_usr[0] = cpu->ReadMemory32(addr); + + addr += 4; } - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(eor_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - LDC_INST: - { - // Instruction not implemented - //LOG_CRITICAL(Core_ARM11, "unimplemented instruction"); - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldc_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - LDM_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ldst_inst* inst_cream = (ldst_inst*)inst_base->component; - inst_cream->get_addr(cpu, inst_cream->inst, addr); - - unsigned int inst = inst_cream->inst; - if (BIT(inst, 22) && !BIT(inst, 15)) { - for (int i = 0; i < 13; i++) { - if(BIT(inst, i)) { - cpu->Reg[i] = cpu->ReadMemory32(addr); - addr += 4; + if (BIT(inst, 14)) { + if (cpu->Mode == USER32MODE) + cpu->Reg[14] = cpu->ReadMemory32(addr); + else + cpu->Reg_usr[1] = cpu->ReadMemory32(addr); + + addr += 4; + } + } else if (!BIT(inst, 22)) { + for (int i = 0; i < 16; i++) { + if (BIT(inst, i)) { + unsigned int ret = cpu->ReadMemory32(addr); + + // For armv5t, should enter thumb when bits[0] is non-zero. + if (i == 15) { + cpu->TFlag = ret & 0x1; + ret &= 0xFFFFFFFE; } - } - if (BIT(inst, 13)) { - if (cpu->Mode == USER32MODE) - cpu->Reg[13] = cpu->ReadMemory32(addr); - else - cpu->Reg_usr[0] = cpu->ReadMemory32(addr); + cpu->Reg[i] = ret; addr += 4; } - if (BIT(inst, 14)) { - if (cpu->Mode == USER32MODE) - cpu->Reg[14] = cpu->ReadMemory32(addr); - else - cpu->Reg_usr[1] = cpu->ReadMemory32(addr); - + } + } else if (BIT(inst, 22) && BIT(inst, 15)) { + for (int i = 0; i < 15; i++) { + if (BIT(inst, i)) { + cpu->Reg[i] = cpu->ReadMemory32(addr); addr += 4; } - } else if (!BIT(inst, 22)) { - for(int i = 0; i < 16; i++ ){ - if(BIT(inst, i)){ - unsigned int ret = cpu->ReadMemory32(addr); - - // For armv5t, should enter thumb when bits[0] is non-zero. - if(i == 15){ - cpu->TFlag = ret & 0x1; - ret &= 0xFFFFFFFE; - } - - cpu->Reg[i] = ret; - addr += 4; - } - } - } else if (BIT(inst, 22) && BIT(inst, 15)) { - for(int i = 0; i < 15; i++ ){ - if(BIT(inst, i)){ - cpu->Reg[i] = cpu->ReadMemory32(addr); - addr += 4; - } - } - - if (CurrentModeHasSPSR) { - cpu->Cpsr = cpu->Spsr_copy; - cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F); - LOAD_NZCVT; - } - - cpu->Reg[15] = cpu->ReadMemory32(addr); } - if (BIT(inst, 15)) { - INC_PC(sizeof(ldst_inst)); - goto DISPATCH; + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F); + LOAD_NZCVT; } + + cpu->Reg[15] = cpu->ReadMemory32(addr); + } + + if (BIT(inst, 15)) { + INC_PC(sizeof(ldst_inst)); + goto DISPATCH; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; } - SXTH_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - sxth_inst* inst_cream = (sxth_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +SXTH_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + sxth_inst* inst_cream = (sxth_inst*)inst_base->component; - unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate); - if (BIT(operand2, 15)) { - operand2 |= 0xffff0000; - } else { - operand2 &= 0xffff; - } - RD = operand2; + unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate); + if (BIT(operand2, 15)) { + operand2 |= 0xffff0000; + } else { + operand2 &= 0xffff; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(sxth_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - LDR_INST: - { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + RD = operand2; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(sxth_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +LDR_INST : { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr); + + unsigned int value = cpu->ReadMemory32(addr); + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; + + if (BITS(inst_cream->inst, 12, 15) == 15) { + // For armv5t, should enter thumb when bits[0] is non-zero. + cpu->TFlag = value & 0x1; + cpu->Reg[15] &= 0xFFFFFFFE; + INC_PC(sizeof(ldst_inst)); + goto DISPATCH; + } + + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +LDRCOND_INST : { + if (CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr); unsigned int value = cpu->ReadMemory32(addr); @@ -1726,2546 +2150,2433 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { INC_PC(sizeof(ldst_inst)); goto DISPATCH; } + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +UXTH_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + uxth_inst* inst_cream = (uxth_inst*)inst_base->component; + RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(uxth_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +UXTAH_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + uxtah_inst* inst_cream = (uxtah_inst*)inst_base->component; + unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff; - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - LDRCOND_INST: - { - if (CondPassed(cpu, inst_base->cond)) { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - inst_cream->get_addr(cpu, inst_cream->inst, addr); - - unsigned int value = cpu->ReadMemory32(addr); - cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; - - if (BITS(inst_cream->inst, 12, 15) == 15) { - // For armv5t, should enter thumb when bits[0] is non-zero. - cpu->TFlag = value & 0x1; - cpu->Reg[15] &= 0xFFFFFFFE; - INC_PC(sizeof(ldst_inst)); - goto DISPATCH; - } - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - UXTH_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - uxth_inst* inst_cream = (uxth_inst*)inst_base->component; - RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff; - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(uxth_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - UXTAH_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - uxtah_inst* inst_cream = (uxtah_inst*)inst_base->component; - unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff; - - RD = RN + operand2; - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(uxtah_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - LDRB_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ldst_inst* inst_cream = (ldst_inst*)inst_base->component; - inst_cream->get_addr(cpu, inst_cream->inst, addr); - - cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory8(addr); - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; + RD = RN + operand2; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(uxtah_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +LDRB_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr); + + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory8(addr); } - LDRBT_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ldst_inst* inst_cream = (ldst_inst*)inst_base->component; - inst_cream->get_addr(cpu, inst_cream->inst, addr); + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +LDRBT_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr); - const u32 dest_index = BITS(inst_cream->inst, 12, 15); - const u32 previous_mode = cpu->Mode; + const u32 dest_index = BITS(inst_cream->inst, 12, 15); + const u32 previous_mode = cpu->Mode; - cpu->ChangePrivilegeMode(USER32MODE); - const u8 value = cpu->ReadMemory8(addr); - cpu->ChangePrivilegeMode(previous_mode); + cpu->ChangePrivilegeMode(USER32MODE); + const u8 value = cpu->ReadMemory8(addr); + cpu->ChangePrivilegeMode(previous_mode); - cpu->Reg[dest_index] = value; - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - LDRD_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ldst_inst* inst_cream = (ldst_inst*)inst_base->component; - // Should check if RD is even-numbered, Rd != 14, addr[0:1] == 0, (CP15_reg1_U == 1 || addr[2] == 0) - inst_cream->get_addr(cpu, inst_cream->inst, addr); - - // The 3DS doesn't have LPAE (Large Physical Access Extension), so it - // wouldn't do this as a single read. - cpu->Reg[BITS(inst_cream->inst, 12, 15) + 0] = cpu->ReadMemory32(addr); - cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1] = cpu->ReadMemory32(addr + 4); - - // No dispatch since this operation should not modify R15 - } - cpu->Reg[15] += 4; - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; + cpu->Reg[dest_index] = value; } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +LDRD_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + // Should check if RD is even-numbered, Rd != 14, addr[0:1] == 0, (CP15_reg1_U == 1 || + // addr[2] == 0) + inst_cream->get_addr(cpu, inst_cream->inst, addr); - LDREX_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - unsigned int read_addr = RN; - - cpu->SetExclusiveMemoryAddress(read_addr); + // The 3DS doesn't have LPAE (Large Physical Access Extension), so it + // wouldn't do this as a single read. + cpu->Reg[BITS(inst_cream->inst, 12, 15) + 0] = cpu->ReadMemory32(addr); + cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1] = cpu->ReadMemory32(addr + 4); - RD = cpu->ReadMemory32(read_addr); - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; + // No dispatch since this operation should not modify R15 } - LDREXB_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - unsigned int read_addr = RN; + cpu->Reg[15] += 4; + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - cpu->SetExclusiveMemoryAddress(read_addr); +LDREX_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int read_addr = RN; - RD = cpu->ReadMemory8(read_addr); - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; + cpu->SetExclusiveMemoryAddress(read_addr); + + RD = cpu->ReadMemory32(read_addr); } - LDREXH_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - unsigned int read_addr = RN; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +LDREXB_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int read_addr = RN; - cpu->SetExclusiveMemoryAddress(read_addr); + cpu->SetExclusiveMemoryAddress(read_addr); - RD = cpu->ReadMemory16(read_addr); - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; + RD = cpu->ReadMemory8(read_addr); } - LDREXD_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - unsigned int read_addr = RN; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +LDREXH_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int read_addr = RN; - cpu->SetExclusiveMemoryAddress(read_addr); + cpu->SetExclusiveMemoryAddress(read_addr); - RD = cpu->ReadMemory32(read_addr); - RD2 = cpu->ReadMemory32(read_addr + 4); - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - LDRH_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ldst_inst* inst_cream = (ldst_inst*)inst_base->component; - inst_cream->get_addr(cpu, inst_cream->inst, addr); - - cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory16(addr); - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - LDRSB_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ldst_inst* inst_cream = (ldst_inst*)inst_base->component; - inst_cream->get_addr(cpu, inst_cream->inst, addr); - unsigned int value = cpu->ReadMemory8(addr); - if (BIT(value, 7)) { - value |= 0xffffff00; - } - cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - LDRSH_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ldst_inst* inst_cream = (ldst_inst*)inst_base->component; - inst_cream->get_addr(cpu, inst_cream->inst, addr); - - unsigned int value = cpu->ReadMemory16(addr); - if (BIT(value, 15)) { - value |= 0xffff0000; - } - cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; + RD = cpu->ReadMemory16(read_addr); } - LDRT_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ldst_inst* inst_cream = (ldst_inst*)inst_base->component; - inst_cream->get_addr(cpu, inst_cream->inst, addr); + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +LDREXD_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int read_addr = RN; - const u32 dest_index = BITS(inst_cream->inst, 12, 15); - const u32 previous_mode = cpu->Mode; + cpu->SetExclusiveMemoryAddress(read_addr); - cpu->ChangePrivilegeMode(USER32MODE); - const u32 value = cpu->ReadMemory32(addr); - cpu->ChangePrivilegeMode(previous_mode); + RD = cpu->ReadMemory32(read_addr); + RD2 = cpu->ReadMemory32(read_addr + 4); + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +LDRH_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr); - cpu->Reg[dest_index] = value; + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory16(addr); + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +LDRSB_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr); + unsigned int value = cpu->ReadMemory8(addr); + if (BIT(value, 7)) { + value |= 0xffffff00; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; } - MCR_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - mcr_inst* inst_cream = (mcr_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +LDRSH_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr); - unsigned int inst = inst_cream->inst; - if (inst_cream->Rd == 15) { - DEBUG_MSG; - } else { - if (inst_cream->cp_num == 15) - cpu->WriteCP15Register(RD, CRn, OPCODE_1, CRm, OPCODE_2); - } + unsigned int value = cpu->ReadMemory16(addr); + if (BIT(value, 15)) { + value |= 0xffff0000; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(mcr_inst)); - FETCH_INST; - GOTO_NEXT_INST; + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +LDRT_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr); + + const u32 dest_index = BITS(inst_cream->inst, 12, 15); + const u32 previous_mode = cpu->Mode; - MCRR_INST: - { - // Stubbed, as the MPCore doesn't have any registers that are accessible - // through this instruction. - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component; + cpu->ChangePrivilegeMode(USER32MODE); + const u32 value = cpu->ReadMemory32(addr); + cpu->ChangePrivilegeMode(previous_mode); - LOG_ERROR(Core_ARM11, "MCRR executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u", - inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, inst_cream->rt2); + cpu->Reg[dest_index] = value; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +MCR_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + mcr_inst* inst_cream = (mcr_inst*)inst_base->component; + + unsigned int inst = inst_cream->inst; + if (inst_cream->Rd == 15) { + DEBUG_MSG; + } else { + if (inst_cream->cp_num == 15) + cpu->WriteCP15Register(RD, CRn, OPCODE_1, CRm, OPCODE_2); } + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(mcr_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} + +MCRR_INST : { + // Stubbed, as the MPCore doesn't have any registers that are accessible + // through this instruction. + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component; - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(mcrr_inst)); - FETCH_INST; - GOTO_NEXT_INST; + LOG_ERROR(Core_ARM11, "MCRR executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u", + inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, + inst_cream->rt2); } - MLA_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - mla_inst* inst_cream = (mla_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(mcrr_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - u64 rm = RM; - u64 rs = RS; - u64 rn = RN; +MLA_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + mla_inst* inst_cream = (mla_inst*)inst_base->component; - RD = static_cast<u32>((rm * rs + rn) & 0xffffffff); - if (inst_cream->S) { - UPDATE_NFLAG(RD); - UPDATE_ZFLAG(RD); - } + u64 rm = RM; + u64 rs = RS; + u64 rn = RN; + + RD = static_cast<u32>((rm * rs + rn) & 0xffffffff); + if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(mla_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - MOV_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - mov_inst* inst_cream = (mov_inst*)inst_base->component; - - RD = SHIFTER_OPERAND; - if (inst_cream->S && (inst_cream->Rd == 15)) { - if (CurrentModeHasSPSR) { - cpu->Cpsr = cpu->Spsr_copy; - cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); - LOAD_NZCVT; - } - } else if (inst_cream->S) { - UPDATE_NFLAG(RD); - UPDATE_ZFLAG(RD); - UPDATE_CFLAG_WITH_SC; - } - if (inst_cream->Rd == 15) { - INC_PC(sizeof(mov_inst)); - goto DISPATCH; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(mla_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +MOV_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + mov_inst* inst_cream = (mov_inst*)inst_base->component; + + RD = SHIFTER_OPERAND; + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); + LOAD_NZCVT; } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + UPDATE_CFLAG_WITH_SC; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(mov_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - MRC_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - mrc_inst* inst_cream = (mrc_inst*)inst_base->component; - - if (inst_cream->cp_num == 15) { - const uint32_t value = cpu->ReadCP15Register(CRn, OPCODE_1, CRm, OPCODE_2); - - if (inst_cream->Rd == 15) { - cpu->Cpsr = (cpu->Cpsr & ~0xF0000000) | (value & 0xF0000000); - LOAD_NZCVT; - } else { - RD = value; - } - } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(mov_inst)); + goto DISPATCH; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(mrc_inst)); - FETCH_INST; - GOTO_NEXT_INST; } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(mov_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +MRC_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + mrc_inst* inst_cream = (mrc_inst*)inst_base->component; - MRRC_INST: - { - // Stubbed, as the MPCore doesn't have any registers that are accessible - // through this instruction. - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component; + if (inst_cream->cp_num == 15) { + const uint32_t value = cpu->ReadCP15Register(CRn, OPCODE_1, CRm, OPCODE_2); - LOG_ERROR(Core_ARM11, "MRRC executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u", - inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, inst_cream->rt2); + if (inst_cream->Rd == 15) { + cpu->Cpsr = (cpu->Cpsr & ~0xF0000000) | (value & 0xF0000000); + LOAD_NZCVT; + } else { + RD = value; + } } + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(mrc_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} + +MRRC_INST : { + // Stubbed, as the MPCore doesn't have any registers that are accessible + // through this instruction. + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component; - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(mcrr_inst)); - FETCH_INST; - GOTO_NEXT_INST; + LOG_ERROR(Core_ARM11, "MRRC executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u", + inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, + inst_cream->rt2); } - MRS_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - mrs_inst* inst_cream = (mrs_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(mcrr_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} + +MRS_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + mrs_inst* inst_cream = (mrs_inst*)inst_base->component; - if (inst_cream->R) { - RD = cpu->Spsr_copy; - } else { - SAVE_NZCVT; - RD = cpu->Cpsr; - } + if (inst_cream->R) { + RD = cpu->Spsr_copy; + } else { + SAVE_NZCVT; + RD = cpu->Cpsr; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(mrs_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - MSR_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - msr_inst* inst_cream = (msr_inst*)inst_base->component; - const u32 UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020; - unsigned int inst = inst_cream->inst; - unsigned int operand; - - if (BIT(inst, 25)) { - int rot_imm = BITS(inst, 8, 11) * 2; - operand = ROTATE_RIGHT_32(BITS(inst, 0, 7), rot_imm); + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(mrs_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +MSR_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + msr_inst* inst_cream = (msr_inst*)inst_base->component; + const u32 UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020; + unsigned int inst = inst_cream->inst; + unsigned int operand; + + if (BIT(inst, 25)) { + int rot_imm = BITS(inst, 8, 11) * 2; + operand = ROTATE_RIGHT_32(BITS(inst, 0, 7), rot_imm); + } else { + operand = cpu->Reg[BITS(inst, 0, 3)]; + } + u32 byte_mask = (BIT(inst, 16) ? 0xff : 0) | (BIT(inst, 17) ? 0xff00 : 0) | + (BIT(inst, 18) ? 0xff0000 : 0) | (BIT(inst, 19) ? 0xff000000 : 0); + u32 mask = 0; + if (!inst_cream->R) { + if (cpu->InAPrivilegedMode()) { + if ((operand & StateMask) != 0) { + /// UNPREDICTABLE + DEBUG_MSG; + } else + mask = byte_mask & (UserMask | PrivMask); } else { - operand = cpu->Reg[BITS(inst, 0, 3)]; + mask = byte_mask & UserMask; } - u32 byte_mask = (BIT(inst, 16) ? 0xff : 0) | (BIT(inst, 17) ? 0xff00 : 0) - | (BIT(inst, 18) ? 0xff0000 : 0) | (BIT(inst, 19) ? 0xff000000 : 0); - u32 mask = 0; - if (!inst_cream->R) { - if (cpu->InAPrivilegedMode()) { - if ((operand & StateMask) != 0) { - /// UNPREDICTABLE - DEBUG_MSG; - } else - mask = byte_mask & (UserMask | PrivMask); - } else { - mask = byte_mask & UserMask; - } - SAVE_NZCVT; + SAVE_NZCVT; - cpu->Cpsr = (cpu->Cpsr & ~mask) | (operand & mask); - cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F); - LOAD_NZCVT; - } else { - if (CurrentModeHasSPSR) { - mask = byte_mask & (UserMask | PrivMask | StateMask); - cpu->Spsr_copy = (cpu->Spsr_copy & ~mask) | (operand & mask); - } + cpu->Cpsr = (cpu->Cpsr & ~mask) | (operand & mask); + cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F); + LOAD_NZCVT; + } else { + if (CurrentModeHasSPSR) { + mask = byte_mask & (UserMask | PrivMask | StateMask); + cpu->Spsr_copy = (cpu->Spsr_copy & ~mask) | (operand & mask); } } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(msr_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - MUL_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - mul_inst* inst_cream = (mul_inst*)inst_base->component; - - u64 rm = RM; - u64 rs = RS; - RD = static_cast<u32>((rm * rs) & 0xffffffff); - if (inst_cream->S) { - UPDATE_NFLAG(RD); - UPDATE_ZFLAG(RD); - } + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(msr_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +MUL_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + mul_inst* inst_cream = (mul_inst*)inst_base->component; + + u64 rm = RM; + u64 rs = RS; + RD = static_cast<u32>((rm * rs) & 0xffffffff); + if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(mul_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - MVN_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - mvn_inst* const inst_cream = (mvn_inst*)inst_base->component; - - RD = ~SHIFTER_OPERAND; - - if (inst_cream->S && (inst_cream->Rd == 15)) { - if (CurrentModeHasSPSR) { - cpu->Cpsr = cpu->Spsr_copy; - cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); - LOAD_NZCVT; - } - } else if (inst_cream->S) { - UPDATE_NFLAG(RD); - UPDATE_ZFLAG(RD); - UPDATE_CFLAG_WITH_SC; - } - if (inst_cream->Rd == 15) { - INC_PC(sizeof(mvn_inst)); - goto DISPATCH; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(mul_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +MVN_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + mvn_inst* const inst_cream = (mvn_inst*)inst_base->component; + + RD = ~SHIFTER_OPERAND; + + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); + LOAD_NZCVT; } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + UPDATE_CFLAG_WITH_SC; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(mvn_inst)); + goto DISPATCH; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(mvn_inst)); - FETCH_INST; - GOTO_NEXT_INST; } - ORR_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - orr_inst* const inst_cream = (orr_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(mvn_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +ORR_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + orr_inst* const inst_cream = (orr_inst*)inst_base->component; - u32 lop = RN; - u32 rop = SHIFTER_OPERAND; + u32 lop = RN; + u32 rop = SHIFTER_OPERAND; - if (inst_cream->Rn == 15) - lop += 2 * cpu->GetInstructionSize(); + if (inst_cream->Rn == 15) + lop += 2 * cpu->GetInstructionSize(); - RD = lop | rop; + RD = lop | rop; - if (inst_cream->S && (inst_cream->Rd == 15)) { - if (CurrentModeHasSPSR) { - cpu->Cpsr = cpu->Spsr_copy; - cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); - LOAD_NZCVT; - } - } else if (inst_cream->S) { - UPDATE_NFLAG(RD); - UPDATE_ZFLAG(RD); - UPDATE_CFLAG_WITH_SC; - } - if (inst_cream->Rd == 15) { - INC_PC(sizeof(orr_inst)); - goto DISPATCH; + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); + LOAD_NZCVT; } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + UPDATE_CFLAG_WITH_SC; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(orr_inst)); + goto DISPATCH; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(orr_inst)); - FETCH_INST; - GOTO_NEXT_INST; } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(orr_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} + +NOP_INST : { + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC_STUB; + FETCH_INST; + GOTO_NEXT_INST; +} - NOP_INST: - { - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC_STUB; - FETCH_INST; - GOTO_NEXT_INST; +PKHBT_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + pkh_inst* inst_cream = (pkh_inst*)inst_base->component; + RD = (RN & 0xFFFF) | ((RM << inst_cream->imm) & 0xFFFF0000); } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(pkh_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - PKHBT_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - pkh_inst *inst_cream = (pkh_inst *)inst_base->component; - RD = (RN & 0xFFFF) | ((RM << inst_cream->imm) & 0xFFFF0000); - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(pkh_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - - PKHTB_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - pkh_inst *inst_cream = (pkh_inst *)inst_base->component; - int shift_imm = inst_cream->imm ? inst_cream->imm : 31; - RD = ((static_cast<s32>(RM) >> shift_imm) & 0xFFFF) | (RN & 0xFFFF0000); - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(pkh_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - - PLD_INST: - { - // Not implemented. PLD is a hint instruction, so it's optional. - - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(pld_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - - QADD_INST: - QDADD_INST: - QDSUB_INST: - QSUB_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; - const u8 op1 = inst_cream->op1; - const u32 rm_val = RM; - const u32 rn_val = RN; +PKHTB_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + pkh_inst* inst_cream = (pkh_inst*)inst_base->component; + int shift_imm = inst_cream->imm ? inst_cream->imm : 31; + RD = ((static_cast<s32>(RM) >> shift_imm) & 0xFFFF) | (RN & 0xFFFF0000); + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(pkh_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - u32 result = 0; +PLD_INST : { + // Not implemented. PLD is a hint instruction, so it's optional. - // QADD - if (op1 == 0x00) { - result = rm_val + rn_val; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(pld_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - if (AddOverflow(rm_val, rn_val, result)) { - result = POS(result) ? 0x80000000 : 0x7FFFFFFF; - cpu->Cpsr |= (1 << 27); - } - } - // QSUB - else if (op1 == 0x01) { - result = rm_val - rn_val; +QADD_INST: +QDADD_INST: +QDSUB_INST: +QSUB_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + const u8 op1 = inst_cream->op1; + const u32 rm_val = RM; + const u32 rn_val = RN; - if (SubOverflow(rm_val, rn_val, result)) { - result = POS(result) ? 0x80000000 : 0x7FFFFFFF; - cpu->Cpsr |= (1 << 27); - } - } - // QDADD - else if (op1 == 0x02) { - u32 mul = (rn_val * 2); + u32 result = 0; - if (AddOverflow(rn_val, rn_val, rn_val * 2)) { - mul = POS(mul) ? 0x80000000 : 0x7FFFFFFF; - cpu->Cpsr |= (1 << 27); - } + // QADD + if (op1 == 0x00) { + result = rm_val + rn_val; - result = mul + rm_val; + if (AddOverflow(rm_val, rn_val, result)) { + result = POS(result) ? 0x80000000 : 0x7FFFFFFF; + cpu->Cpsr |= (1 << 27); + } + } + // QSUB + else if (op1 == 0x01) { + result = rm_val - rn_val; - if (AddOverflow(rm_val, mul, result)) { - result = POS(result) ? 0x80000000 : 0x7FFFFFFF; - cpu->Cpsr |= (1 << 27); - } + if (SubOverflow(rm_val, rn_val, result)) { + result = POS(result) ? 0x80000000 : 0x7FFFFFFF; + cpu->Cpsr |= (1 << 27); } - // QDSUB - else if (op1 == 0x03) { - u32 mul = (rn_val * 2); + } + // QDADD + else if (op1 == 0x02) { + u32 mul = (rn_val * 2); - if (AddOverflow(rn_val, rn_val, mul)) { - mul = POS(mul) ? 0x80000000 : 0x7FFFFFFF; - cpu->Cpsr |= (1 << 27); - } + if (AddOverflow(rn_val, rn_val, rn_val * 2)) { + mul = POS(mul) ? 0x80000000 : 0x7FFFFFFF; + cpu->Cpsr |= (1 << 27); + } - result = rm_val - mul; + result = mul + rm_val; - if (SubOverflow(rm_val, mul, result)) { - result = POS(result) ? 0x80000000 : 0x7FFFFFFF; - cpu->Cpsr |= (1 << 27); - } + if (AddOverflow(rm_val, mul, result)) { + result = POS(result) ? 0x80000000 : 0x7FFFFFFF; + cpu->Cpsr |= (1 << 27); } - - RD = result; } + // QDSUB + else if (op1 == 0x03) { + u32 mul = (rn_val * 2); - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - - QADD8_INST: - QADD16_INST: - QADDSUBX_INST: - QSUB8_INST: - QSUB16_INST: - QSUBADDX_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; - const u16 rm_lo = (RM & 0xFFFF); - const u16 rm_hi = ((RM >> 16) & 0xFFFF); - const u16 rn_lo = (RN & 0xFFFF); - const u16 rn_hi = ((RN >> 16) & 0xFFFF); - const u8 op2 = inst_cream->op2; - - u16 lo_result = 0; - u16 hi_result = 0; - - // QADD16 - if (op2 == 0x00) { - lo_result = ARMul_SignedSaturatedAdd16(rn_lo, rm_lo); - hi_result = ARMul_SignedSaturatedAdd16(rn_hi, rm_hi); - } - // QASX - else if (op2 == 0x01) { - lo_result = ARMul_SignedSaturatedSub16(rn_lo, rm_hi); - hi_result = ARMul_SignedSaturatedAdd16(rn_hi, rm_lo); - } - // QSAX - else if (op2 == 0x02) { - lo_result = ARMul_SignedSaturatedAdd16(rn_lo, rm_hi); - hi_result = ARMul_SignedSaturatedSub16(rn_hi, rm_lo); - } - // QSUB16 - else if (op2 == 0x03) { - lo_result = ARMul_SignedSaturatedSub16(rn_lo, rm_lo); - hi_result = ARMul_SignedSaturatedSub16(rn_hi, rm_hi); - } - // QADD8 - else if (op2 == 0x04) { - lo_result = ARMul_SignedSaturatedAdd8(rn_lo & 0xFF, rm_lo & 0xFF) | - ARMul_SignedSaturatedAdd8(rn_lo >> 8, rm_lo >> 8) << 8; - hi_result = ARMul_SignedSaturatedAdd8(rn_hi & 0xFF, rm_hi & 0xFF) | - ARMul_SignedSaturatedAdd8(rn_hi >> 8, rm_hi >> 8) << 8; + if (AddOverflow(rn_val, rn_val, mul)) { + mul = POS(mul) ? 0x80000000 : 0x7FFFFFFF; + cpu->Cpsr |= (1 << 27); } - // QSUB8 - else if (op2 == 0x07) { - lo_result = ARMul_SignedSaturatedSub8(rn_lo & 0xFF, rm_lo & 0xFF) | - ARMul_SignedSaturatedSub8(rn_lo >> 8, rm_lo >> 8) << 8; - hi_result = ARMul_SignedSaturatedSub8(rn_hi & 0xFF, rm_hi & 0xFF) | - ARMul_SignedSaturatedSub8(rn_hi >> 8, rm_hi >> 8) << 8; + + result = rm_val - mul; + + if (SubOverflow(rm_val, mul, result)) { + result = POS(result) ? 0x80000000 : 0x7FFFFFFF; + cpu->Cpsr |= (1 << 27); } + } - RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16); + RD = result; + } + + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} + +QADD8_INST: +QADD16_INST: +QADDSUBX_INST: +QSUB8_INST: +QSUB16_INST: +QSUBADDX_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + const u16 rm_lo = (RM & 0xFFFF); + const u16 rm_hi = ((RM >> 16) & 0xFFFF); + const u16 rn_lo = (RN & 0xFFFF); + const u16 rn_hi = ((RN >> 16) & 0xFFFF); + const u8 op2 = inst_cream->op2; + + u16 lo_result = 0; + u16 hi_result = 0; + + // QADD16 + if (op2 == 0x00) { + lo_result = ARMul_SignedSaturatedAdd16(rn_lo, rm_lo); + hi_result = ARMul_SignedSaturatedAdd16(rn_hi, rm_hi); + } + // QASX + else if (op2 == 0x01) { + lo_result = ARMul_SignedSaturatedSub16(rn_lo, rm_hi); + hi_result = ARMul_SignedSaturatedAdd16(rn_hi, rm_lo); + } + // QSAX + else if (op2 == 0x02) { + lo_result = ARMul_SignedSaturatedAdd16(rn_lo, rm_hi); + hi_result = ARMul_SignedSaturatedSub16(rn_hi, rm_lo); + } + // QSUB16 + else if (op2 == 0x03) { + lo_result = ARMul_SignedSaturatedSub16(rn_lo, rm_lo); + hi_result = ARMul_SignedSaturatedSub16(rn_hi, rm_hi); + } + // QADD8 + else if (op2 == 0x04) { + lo_result = ARMul_SignedSaturatedAdd8(rn_lo & 0xFF, rm_lo & 0xFF) | + ARMul_SignedSaturatedAdd8(rn_lo >> 8, rm_lo >> 8) << 8; + hi_result = ARMul_SignedSaturatedAdd8(rn_hi & 0xFF, rm_hi & 0xFF) | + ARMul_SignedSaturatedAdd8(rn_hi >> 8, rm_hi >> 8) << 8; + } + // QSUB8 + else if (op2 == 0x07) { + lo_result = ARMul_SignedSaturatedSub8(rn_lo & 0xFF, rm_lo & 0xFF) | + ARMul_SignedSaturatedSub8(rn_lo >> 8, rm_lo >> 8) << 8; + hi_result = ARMul_SignedSaturatedSub8(rn_hi & 0xFF, rm_hi & 0xFF) | + ARMul_SignedSaturatedSub8(rn_hi >> 8, rm_hi >> 8) << 8; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; + RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16); } - REV_INST: - REV16_INST: - REVSH_INST: - { + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - rev_inst* const inst_cream = (rev_inst*)inst_base->component; +REV_INST: +REV16_INST: +REVSH_INST : { - const u8 op1 = inst_cream->op1; - const u8 op2 = inst_cream->op2; + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + rev_inst* const inst_cream = (rev_inst*)inst_base->component; - // REV - if (op1 == 0x03 && op2 == 0x01) { - RD = ((RM & 0xFF) << 24) | (((RM >> 8) & 0xFF) << 16) | (((RM >> 16) & 0xFF) << 8) | ((RM >> 24) & 0xFF); - } - // REV16 - else if (op1 == 0x03 && op2 == 0x05) { - RD = ((RM & 0xFF) << 8) | ((RM & 0xFF00) >> 8) | ((RM & 0xFF0000) << 8) | ((RM & 0xFF000000) >> 8); - } - // REVSH - else if (op1 == 0x07 && op2 == 0x05) { - RD = ((RM & 0xFF) << 8) | ((RM & 0xFF00) >> 8); - if (RD & 0x8000) - RD |= 0xffff0000; - } - } + const u8 op1 = inst_cream->op1; + const u8 op2 = inst_cream->op2; - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(rev_inst)); - FETCH_INST; - GOTO_NEXT_INST; + // REV + if (op1 == 0x03 && op2 == 0x01) { + RD = ((RM & 0xFF) << 24) | (((RM >> 8) & 0xFF) << 16) | (((RM >> 16) & 0xFF) << 8) | + ((RM >> 24) & 0xFF); + } + // REV16 + else if (op1 == 0x03 && op2 == 0x05) { + RD = ((RM & 0xFF) << 8) | ((RM & 0xFF00) >> 8) | ((RM & 0xFF0000) << 8) | + ((RM & 0xFF000000) >> 8); + } + // REVSH + else if (op1 == 0x07 && op2 == 0x05) { + RD = ((RM & 0xFF) << 8) | ((RM & 0xFF00) >> 8); + if (RD & 0x8000) + RD |= 0xffff0000; + } } - RFE_INST: - { - // RFE is unconditional - ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(rev_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - u32 address = 0; - inst_cream->get_addr(cpu, inst_cream->inst, address); +RFE_INST : { + // RFE is unconditional + ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; - cpu->Cpsr = cpu->ReadMemory32(address); - cpu->Reg[15] = cpu->ReadMemory32(address + 4); + u32 address = 0; + inst_cream->get_addr(cpu, inst_cream->inst, address); - INC_PC(sizeof(ldst_inst)); - goto DISPATCH; - } + cpu->Cpsr = cpu->ReadMemory32(address); + cpu->Reg[15] = cpu->ReadMemory32(address + 4); - RSB_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - rsb_inst* const inst_cream = (rsb_inst*)inst_base->component; + INC_PC(sizeof(ldst_inst)); + goto DISPATCH; +} - u32 rn_val = RN; - if (inst_cream->Rn == 15) - rn_val += 2 * cpu->GetInstructionSize(); +RSB_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + rsb_inst* const inst_cream = (rsb_inst*)inst_base->component; - bool carry; - bool overflow; - RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, 1, &carry, &overflow); + u32 rn_val = RN; + if (inst_cream->Rn == 15) + rn_val += 2 * cpu->GetInstructionSize(); - if (inst_cream->S && (inst_cream->Rd == 15)) { - if (CurrentModeHasSPSR) { - cpu->Cpsr = cpu->Spsr_copy; - cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); - LOAD_NZCVT; - } - } else if (inst_cream->S) { - UPDATE_NFLAG(RD); - UPDATE_ZFLAG(RD); - cpu->CFlag = carry; - cpu->VFlag = overflow; + bool carry; + bool overflow; + RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, 1, &carry, &overflow); + + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); + LOAD_NZCVT; } - if (inst_cream->Rd == 15) { - INC_PC(sizeof(rsb_inst)); - goto DISPATCH; + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(rsb_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(rsb_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +RSC_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + rsc_inst* const inst_cream = (rsc_inst*)inst_base->component; + + u32 rn_val = RN; + if (inst_cream->Rn == 15) + rn_val += 2 * cpu->GetInstructionSize(); + + bool carry; + bool overflow; + RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); + + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); + LOAD_NZCVT; } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(rsb_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - RSC_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - rsc_inst* const inst_cream = (rsc_inst*)inst_base->component; - - u32 rn_val = RN; - if (inst_cream->Rn == 15) - rn_val += 2 * cpu->GetInstructionSize(); - - bool carry; - bool overflow; - RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); - - if (inst_cream->S && (inst_cream->Rd == 15)) { - if (CurrentModeHasSPSR) { - cpu->Cpsr = cpu->Spsr_copy; - cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); - LOAD_NZCVT; - } - } else if (inst_cream->S) { - UPDATE_NFLAG(RD); - UPDATE_ZFLAG(RD); - cpu->CFlag = carry; - cpu->VFlag = overflow; + if (inst_cream->Rd == 15) { + INC_PC(sizeof(rsc_inst)); + goto DISPATCH; + } + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(rsc_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} + +SADD8_INST: +SSUB8_INST: +SADD16_INST: +SADDSUBX_INST: +SSUBADDX_INST: +SSUB16_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + const u8 op2 = inst_cream->op2; + + if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) { + const s16 rn_lo = (RN & 0xFFFF); + const s16 rn_hi = ((RN >> 16) & 0xFFFF); + const s16 rm_lo = (RM & 0xFFFF); + const s16 rm_hi = ((RM >> 16) & 0xFFFF); + + s32 lo_result = 0; + s32 hi_result = 0; + + // SADD16 + if (inst_cream->op2 == 0x00) { + lo_result = (rn_lo + rm_lo); + hi_result = (rn_hi + rm_hi); } - if (inst_cream->Rd == 15) { - INC_PC(sizeof(rsc_inst)); - goto DISPATCH; + // SASX + else if (op2 == 0x01) { + lo_result = (rn_lo - rm_hi); + hi_result = (rn_hi + rm_lo); + } + // SSAX + else if (op2 == 0x02) { + lo_result = (rn_lo + rm_hi); + hi_result = (rn_hi - rm_lo); + } + // SSUB16 + else if (op2 == 0x03) { + lo_result = (rn_lo - rm_lo); + hi_result = (rn_hi - rm_hi); } - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(rsc_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - - SADD8_INST: - SSUB8_INST: - SADD16_INST: - SADDSUBX_INST: - SSUBADDX_INST: - SSUB16_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; - const u8 op2 = inst_cream->op2; - - if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) { - const s16 rn_lo = (RN & 0xFFFF); - const s16 rn_hi = ((RN >> 16) & 0xFFFF); - const s16 rm_lo = (RM & 0xFFFF); - const s16 rm_hi = ((RM >> 16) & 0xFFFF); - - s32 lo_result = 0; - s32 hi_result = 0; - - // SADD16 - if (inst_cream->op2 == 0x00) { - lo_result = (rn_lo + rm_lo); - hi_result = (rn_hi + rm_hi); - } - // SASX - else if (op2 == 0x01) { - lo_result = (rn_lo - rm_hi); - hi_result = (rn_hi + rm_lo); - } - // SSAX - else if (op2 == 0x02) { - lo_result = (rn_lo + rm_hi); - hi_result = (rn_hi - rm_lo); - } - // SSUB16 - else if (op2 == 0x03) { - lo_result = (rn_lo - rm_lo); - hi_result = (rn_hi - rm_hi); - } - RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16); + RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16); - if (lo_result >= 0) { - cpu->Cpsr |= (1 << 16); - cpu->Cpsr |= (1 << 17); - } else { - cpu->Cpsr &= ~(1 << 16); - cpu->Cpsr &= ~(1 << 17); - } + if (lo_result >= 0) { + cpu->Cpsr |= (1 << 16); + cpu->Cpsr |= (1 << 17); + } else { + cpu->Cpsr &= ~(1 << 16); + cpu->Cpsr &= ~(1 << 17); + } - if (hi_result >= 0) { - cpu->Cpsr |= (1 << 18); - cpu->Cpsr |= (1 << 19); - } else { - cpu->Cpsr &= ~(1 << 18); - cpu->Cpsr &= ~(1 << 19); - } + if (hi_result >= 0) { + cpu->Cpsr |= (1 << 18); + cpu->Cpsr |= (1 << 19); + } else { + cpu->Cpsr &= ~(1 << 18); + cpu->Cpsr &= ~(1 << 19); + } + } else if (op2 == 0x04 || op2 == 0x07) { + s32 lo_val1, lo_val2; + s32 hi_val1, hi_val2; + + // SADD8 + if (op2 == 0x04) { + lo_val1 = (s32)(s8)(RN & 0xFF) + (s32)(s8)(RM & 0xFF); + lo_val2 = (s32)(s8)((RN >> 8) & 0xFF) + (s32)(s8)((RM >> 8) & 0xFF); + hi_val1 = (s32)(s8)((RN >> 16) & 0xFF) + (s32)(s8)((RM >> 16) & 0xFF); + hi_val2 = (s32)(s8)((RN >> 24) & 0xFF) + (s32)(s8)((RM >> 24) & 0xFF); + } + // SSUB8 + else { + lo_val1 = (s32)(s8)(RN & 0xFF) - (s32)(s8)(RM & 0xFF); + lo_val2 = (s32)(s8)((RN >> 8) & 0xFF) - (s32)(s8)((RM >> 8) & 0xFF); + hi_val1 = (s32)(s8)((RN >> 16) & 0xFF) - (s32)(s8)((RM >> 16) & 0xFF); + hi_val2 = (s32)(s8)((RN >> 24) & 0xFF) - (s32)(s8)((RM >> 24) & 0xFF); } - else if (op2 == 0x04 || op2 == 0x07) { - s32 lo_val1, lo_val2; - s32 hi_val1, hi_val2; - - // SADD8 - if (op2 == 0x04) { - lo_val1 = (s32)(s8)(RN & 0xFF) + (s32)(s8)(RM & 0xFF); - lo_val2 = (s32)(s8)((RN >> 8) & 0xFF) + (s32)(s8)((RM >> 8) & 0xFF); - hi_val1 = (s32)(s8)((RN >> 16) & 0xFF) + (s32)(s8)((RM >> 16) & 0xFF); - hi_val2 = (s32)(s8)((RN >> 24) & 0xFF) + (s32)(s8)((RM >> 24) & 0xFF); - } - // SSUB8 - else { - lo_val1 = (s32)(s8)(RN & 0xFF) - (s32)(s8)(RM & 0xFF); - lo_val2 = (s32)(s8)((RN >> 8) & 0xFF) - (s32)(s8)((RM >> 8) & 0xFF); - hi_val1 = (s32)(s8)((RN >> 16) & 0xFF) - (s32)(s8)((RM >> 16) & 0xFF); - hi_val2 = (s32)(s8)((RN >> 24) & 0xFF) - (s32)(s8)((RM >> 24) & 0xFF); - } - RD = ((lo_val1 & 0xFF) | ((lo_val2 & 0xFF) << 8) | ((hi_val1 & 0xFF) << 16) | ((hi_val2 & 0xFF) << 24)); + RD = ((lo_val1 & 0xFF) | ((lo_val2 & 0xFF) << 8) | ((hi_val1 & 0xFF) << 16) | + ((hi_val2 & 0xFF) << 24)); - if (lo_val1 >= 0) - cpu->Cpsr |= (1 << 16); - else - cpu->Cpsr &= ~(1 << 16); + if (lo_val1 >= 0) + cpu->Cpsr |= (1 << 16); + else + cpu->Cpsr &= ~(1 << 16); - if (lo_val2 >= 0) - cpu->Cpsr |= (1 << 17); - else - cpu->Cpsr &= ~(1 << 17); + if (lo_val2 >= 0) + cpu->Cpsr |= (1 << 17); + else + cpu->Cpsr &= ~(1 << 17); - if (hi_val1 >= 0) - cpu->Cpsr |= (1 << 18); - else - cpu->Cpsr &= ~(1 << 18); + if (hi_val1 >= 0) + cpu->Cpsr |= (1 << 18); + else + cpu->Cpsr &= ~(1 << 18); - if (hi_val2 >= 0) - cpu->Cpsr |= (1 << 19); - else - cpu->Cpsr &= ~(1 << 19); - } + if (hi_val2 >= 0) + cpu->Cpsr |= (1 << 19); + else + cpu->Cpsr &= ~(1 << 19); } - - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; } - SBC_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - sbc_inst* const inst_cream = (sbc_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - u32 rn_val = RN; - if (inst_cream->Rn == 15) - rn_val += 2 * cpu->GetInstructionSize(); +SBC_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + sbc_inst* const inst_cream = (sbc_inst*)inst_base->component; - bool carry; - bool overflow; - RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); + u32 rn_val = RN; + if (inst_cream->Rn == 15) + rn_val += 2 * cpu->GetInstructionSize(); - if (inst_cream->S && (inst_cream->Rd == 15)) { - if (CurrentModeHasSPSR) { - cpu->Cpsr = cpu->Spsr_copy; - cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); - LOAD_NZCVT; - } - } else if (inst_cream->S) { - UPDATE_NFLAG(RD); - UPDATE_ZFLAG(RD); - cpu->CFlag = carry; - cpu->VFlag = overflow; - } - if (inst_cream->Rd == 15) { - INC_PC(sizeof(sbc_inst)); - goto DISPATCH; + bool carry; + bool overflow; + RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); + + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); + LOAD_NZCVT; } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; + } + if (inst_cream->Rd == 15) { + INC_PC(sizeof(sbc_inst)); + goto DISPATCH; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(sbc_inst)); - FETCH_INST; - GOTO_NEXT_INST; } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(sbc_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - SEL_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; - - const u32 to = RM; - const u32 from = RN; - const u32 cpsr = cpu->Cpsr; +SEL_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; - u32 result; - if (cpsr & (1 << 16)) - result = from & 0xff; - else - result = to & 0xff; + const u32 to = RM; + const u32 from = RN; + const u32 cpsr = cpu->Cpsr; - if (cpsr & (1 << 17)) - result |= from & 0x0000ff00; - else - result |= to & 0x0000ff00; + u32 result; + if (cpsr & (1 << 16)) + result = from & 0xff; + else + result = to & 0xff; - if (cpsr & (1 << 18)) - result |= from & 0x00ff0000; - else - result |= to & 0x00ff0000; + if (cpsr & (1 << 17)) + result |= from & 0x0000ff00; + else + result |= to & 0x0000ff00; - if (cpsr & (1 << 19)) - result |= from & 0xff000000; - else - result |= to & 0xff000000; + if (cpsr & (1 << 18)) + result |= from & 0x00ff0000; + else + result |= to & 0x00ff0000; - RD = result; - } + if (cpsr & (1 << 19)) + result |= from & 0xff000000; + else + result |= to & 0xff000000; - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; + RD = result; } - SETEND_INST: - { - // SETEND is unconditional - setend_inst* const inst_cream = (setend_inst*)inst_base->component; - const bool big_endian = (inst_cream->set_bigend == 1); + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - if (big_endian) - cpu->Cpsr |= (1 << 9); - else - cpu->Cpsr &= ~(1 << 9); +SETEND_INST : { + // SETEND is unconditional + setend_inst* const inst_cream = (setend_inst*)inst_base->component; + const bool big_endian = (inst_cream->set_bigend == 1); - LOG_WARNING(Core_ARM11, "SETEND %s executed", big_endian ? "BE" : "LE"); + if (big_endian) + cpu->Cpsr |= (1 << 9); + else + cpu->Cpsr &= ~(1 << 9); - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(setend_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } + LOG_WARNING(Core_ARM11, "SETEND %s executed", big_endian ? "BE" : "LE"); - SEV_INST: - { - // Stubbed, as SEV is a hint instruction. - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - LOG_TRACE(Core_ARM11, "SEV executed."); - } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(setend_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC_STUB; - FETCH_INST; - GOTO_NEXT_INST; +SEV_INST : { + // Stubbed, as SEV is a hint instruction. + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + LOG_TRACE(Core_ARM11, "SEV executed."); } - SHADD8_INST: - SHADD16_INST: - SHADDSUBX_INST: - SHSUB8_INST: - SHSUB16_INST: - SHSUBADDX_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC_STUB; + FETCH_INST; + GOTO_NEXT_INST; +} - const u8 op2 = inst_cream->op2; - const u32 rm_val = RM; - const u32 rn_val = RN; +SHADD8_INST: +SHADD16_INST: +SHADDSUBX_INST: +SHSUB8_INST: +SHSUB16_INST: +SHSUBADDX_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; - if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) { - s32 lo_result = 0; - s32 hi_result = 0; + const u8 op2 = inst_cream->op2; + const u32 rm_val = RM; + const u32 rn_val = RN; - // SHADD16 - if (op2 == 0x00) { - lo_result = ((s16)(rn_val & 0xFFFF) + (s16)(rm_val & 0xFFFF)) >> 1; - hi_result = ((s16)((rn_val >> 16) & 0xFFFF) + (s16)((rm_val >> 16) & 0xFFFF)) >> 1; - } - // SHASX - else if (op2 == 0x01) { - lo_result = ((s16)(rn_val & 0xFFFF) - (s16)((rm_val >> 16) & 0xFFFF)) >> 1; - hi_result = ((s16)((rn_val >> 16) & 0xFFFF) + (s16)(rm_val & 0xFFFF)) >> 1; - } - // SHSAX - else if (op2 == 0x02) { - lo_result = ((s16)(rn_val & 0xFFFF) + (s16)((rm_val >> 16) & 0xFFFF)) >> 1; - hi_result = ((s16)((rn_val >> 16) & 0xFFFF) - (s16)(rm_val & 0xFFFF)) >> 1; - } - // SHSUB16 - else if (op2 == 0x03) { - lo_result = ((s16)(rn_val & 0xFFFF) - (s16)(rm_val & 0xFFFF)) >> 1; - hi_result = ((s16)((rn_val >> 16) & 0xFFFF) - (s16)((rm_val >> 16) & 0xFFFF)) >> 1; - } + if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) { + s32 lo_result = 0; + s32 hi_result = 0; - RD = ((lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16)); + // SHADD16 + if (op2 == 0x00) { + lo_result = ((s16)(rn_val & 0xFFFF) + (s16)(rm_val & 0xFFFF)) >> 1; + hi_result = ((s16)((rn_val >> 16) & 0xFFFF) + (s16)((rm_val >> 16) & 0xFFFF)) >> 1; + } + // SHASX + else if (op2 == 0x01) { + lo_result = ((s16)(rn_val & 0xFFFF) - (s16)((rm_val >> 16) & 0xFFFF)) >> 1; + hi_result = ((s16)((rn_val >> 16) & 0xFFFF) + (s16)(rm_val & 0xFFFF)) >> 1; + } + // SHSAX + else if (op2 == 0x02) { + lo_result = ((s16)(rn_val & 0xFFFF) + (s16)((rm_val >> 16) & 0xFFFF)) >> 1; + hi_result = ((s16)((rn_val >> 16) & 0xFFFF) - (s16)(rm_val & 0xFFFF)) >> 1; + } + // SHSUB16 + else if (op2 == 0x03) { + lo_result = ((s16)(rn_val & 0xFFFF) - (s16)(rm_val & 0xFFFF)) >> 1; + hi_result = ((s16)((rn_val >> 16) & 0xFFFF) - (s16)((rm_val >> 16) & 0xFFFF)) >> 1; } - else if (op2 == 0x04 || op2 == 0x07) { - s16 lo_val1, lo_val2; - s16 hi_val1, hi_val2; - // SHADD8 - if (op2 == 0x04) { - lo_val1 = ((s8)(rn_val & 0xFF) + (s8)(rm_val & 0xFF)) >> 1; - lo_val2 = ((s8)((rn_val >> 8) & 0xFF) + (s8)((rm_val >> 8) & 0xFF)) >> 1; + RD = ((lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16)); + } else if (op2 == 0x04 || op2 == 0x07) { + s16 lo_val1, lo_val2; + s16 hi_val1, hi_val2; - hi_val1 = ((s8)((rn_val >> 16) & 0xFF) + (s8)((rm_val >> 16) & 0xFF)) >> 1; - hi_val2 = ((s8)((rn_val >> 24) & 0xFF) + (s8)((rm_val >> 24) & 0xFF)) >> 1; - } - // SHSUB8 - else { - lo_val1 = ((s8)(rn_val & 0xFF) - (s8)(rm_val & 0xFF)) >> 1; - lo_val2 = ((s8)((rn_val >> 8) & 0xFF) - (s8)((rm_val >> 8) & 0xFF)) >> 1; + // SHADD8 + if (op2 == 0x04) { + lo_val1 = ((s8)(rn_val & 0xFF) + (s8)(rm_val & 0xFF)) >> 1; + lo_val2 = ((s8)((rn_val >> 8) & 0xFF) + (s8)((rm_val >> 8) & 0xFF)) >> 1; - hi_val1 = ((s8)((rn_val >> 16) & 0xFF) - (s8)((rm_val >> 16) & 0xFF)) >> 1; - hi_val2 = ((s8)((rn_val >> 24) & 0xFF) - (s8)((rm_val >> 24) & 0xFF)) >> 1; - } - - RD = (lo_val1 & 0xFF) | ((lo_val2 & 0xFF) << 8) | ((hi_val1 & 0xFF) << 16) | ((hi_val2 & 0xFF) << 24); + hi_val1 = ((s8)((rn_val >> 16) & 0xFF) + (s8)((rm_val >> 16) & 0xFF)) >> 1; + hi_val2 = ((s8)((rn_val >> 24) & 0xFF) + (s8)((rm_val >> 24) & 0xFF)) >> 1; } - } - - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - - SMLA_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - smla_inst* inst_cream = (smla_inst*)inst_base->component; - s32 operand1, operand2; - if (inst_cream->x == 0) - operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15); - else - operand1 = (BIT(RM, 31)) ? (BITS(RM, 16, 31) | 0xffff0000) : BITS(RM, 16, 31); + // SHSUB8 + else { + lo_val1 = ((s8)(rn_val & 0xFF) - (s8)(rm_val & 0xFF)) >> 1; + lo_val2 = ((s8)((rn_val >> 8) & 0xFF) - (s8)((rm_val >> 8) & 0xFF)) >> 1; - if (inst_cream->y == 0) - operand2 = (BIT(RS, 15)) ? (BITS(RS, 0, 15) | 0xffff0000) : BITS(RS, 0, 15); - else - operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31); + hi_val1 = ((s8)((rn_val >> 16) & 0xFF) - (s8)((rm_val >> 16) & 0xFF)) >> 1; + hi_val2 = ((s8)((rn_val >> 24) & 0xFF) - (s8)((rm_val >> 24) & 0xFF)) >> 1; + } - u32 product = operand1 * operand2; - u32 result = product + RN; - if (AddOverflow(product, RN, result)) - cpu->Cpsr |= (1 << 27); - RD = result; + RD = (lo_val1 & 0xFF) | ((lo_val2 & 0xFF) << 8) | ((hi_val1 & 0xFF) << 16) | + ((hi_val2 & 0xFF) << 24); } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(smla_inst)); - FETCH_INST; - GOTO_NEXT_INST; } - SMLAD_INST: - SMLSD_INST: - SMUAD_INST: - SMUSD_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; - const u8 op2 = inst_cream->op2; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - u32 rm_val = cpu->Reg[inst_cream->Rm]; - const u32 rn_val = cpu->Reg[inst_cream->Rn]; +SMLA_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + smla_inst* inst_cream = (smla_inst*)inst_base->component; + s32 operand1, operand2; + if (inst_cream->x == 0) + operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15); + else + operand1 = (BIT(RM, 31)) ? (BITS(RM, 16, 31) | 0xffff0000) : BITS(RM, 16, 31); - if (inst_cream->m) - rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16)); + if (inst_cream->y == 0) + operand2 = (BIT(RS, 15)) ? (BITS(RS, 0, 15) | 0xffff0000) : BITS(RS, 0, 15); + else + operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31); + + u32 product = operand1 * operand2; + u32 result = product + RN; + if (AddOverflow(product, RN, result)) + cpu->Cpsr |= (1 << 27); + RD = result; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(smla_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - const s16 rm_lo = (rm_val & 0xFFFF); - const s16 rm_hi = ((rm_val >> 16) & 0xFFFF); - const s16 rn_lo = (rn_val & 0xFFFF); - const s16 rn_hi = ((rn_val >> 16) & 0xFFFF); +SMLAD_INST: +SMLSD_INST: +SMUAD_INST: +SMUSD_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; + const u8 op2 = inst_cream->op2; - const u32 product1 = (rn_lo * rm_lo); - const u32 product2 = (rn_hi * rm_hi); + u32 rm_val = cpu->Reg[inst_cream->Rm]; + const u32 rn_val = cpu->Reg[inst_cream->Rn]; - // SMUAD and SMLAD - if (BIT(op2, 1) == 0) { - u32 rd_val = (product1 + product2); + if (inst_cream->m) + rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16)); - if (inst_cream->Ra != 15) { - rd_val += cpu->Reg[inst_cream->Ra]; + const s16 rm_lo = (rm_val & 0xFFFF); + const s16 rm_hi = ((rm_val >> 16) & 0xFFFF); + const s16 rn_lo = (rn_val & 0xFFFF); + const s16 rn_hi = ((rn_val >> 16) & 0xFFFF); - if (ARMul_AddOverflowQ(product1 + product2, cpu->Reg[inst_cream->Ra])) - cpu->Cpsr |= (1 << 27); - } + const u32 product1 = (rn_lo * rm_lo); + const u32 product2 = (rn_hi * rm_hi); + + // SMUAD and SMLAD + if (BIT(op2, 1) == 0) { + u32 rd_val = (product1 + product2); - RD = rd_val; + if (inst_cream->Ra != 15) { + rd_val += cpu->Reg[inst_cream->Ra]; - if (ARMul_AddOverflowQ(product1, product2)) + if (ARMul_AddOverflowQ(product1 + product2, cpu->Reg[inst_cream->Ra])) cpu->Cpsr |= (1 << 27); } - // SMUSD and SMLSD - else { - u32 rd_val = (product1 - product2); - if (inst_cream->Ra != 15) { - rd_val += cpu->Reg[inst_cream->Ra]; + RD = rd_val; - if (ARMul_AddOverflowQ(product1 - product2, cpu->Reg[inst_cream->Ra])) - cpu->Cpsr |= (1 << 27); - } + if (ARMul_AddOverflowQ(product1, product2)) + cpu->Cpsr |= (1 << 27); + } + // SMUSD and SMLSD + else { + u32 rd_val = (product1 - product2); + + if (inst_cream->Ra != 15) { + rd_val += cpu->Reg[inst_cream->Ra]; - RD = rd_val; + if (ARMul_AddOverflowQ(product1 - product2, cpu->Reg[inst_cream->Ra])) + cpu->Cpsr |= (1 << 27); } - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(smlad_inst)); - FETCH_INST; - GOTO_NEXT_INST; + RD = rd_val; + } } - SMLAL_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - umlal_inst* inst_cream = (umlal_inst*)inst_base->component; - long long int rm = RM; - long long int rs = RS; - if (BIT(rm, 31)) { - rm |= 0xffffffff00000000LL; - } - if (BIT(rs, 31)) { - rs |= 0xffffffff00000000LL; - } - long long int rst = rm * rs; - long long int rdhi32 = RDHI; - long long int hilo = (rdhi32 << 32) + RDLO; - rst += hilo; - RDLO = BITS(rst, 0, 31); - RDHI = BITS(rst, 32, 63); - if (inst_cream->S) { - cpu->NFlag = BIT(RDHI, 31); - cpu->ZFlag = (RDHI == 0 && RDLO == 0); - } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(smlad_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} + +SMLAL_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + umlal_inst* inst_cream = (umlal_inst*)inst_base->component; + long long int rm = RM; + long long int rs = RS; + if (BIT(rm, 31)) { + rm |= 0xffffffff00000000LL; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(umlal_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - - SMLALXY_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component; - - u64 operand1 = RN; - u64 operand2 = RM; - - if (inst_cream->x != 0) - operand1 >>= 16; - if (inst_cream->y != 0) - operand2 >>= 16; - operand1 &= 0xFFFF; - if (operand1 & 0x8000) - operand1 -= 65536; - operand2 &= 0xFFFF; - if (operand2 & 0x8000) - operand2 -= 65536; - - u64 dest = ((u64)RDHI << 32 | RDLO) + (operand1 * operand2); - RDLO = (dest & 0xFFFFFFFF); - RDHI = ((dest >> 32) & 0xFFFFFFFF); + if (BIT(rs, 31)) { + rs |= 0xffffffff00000000LL; + } + long long int rst = rm * rs; + long long int rdhi32 = RDHI; + long long int hilo = (rdhi32 << 32) + RDLO; + rst += hilo; + RDLO = BITS(rst, 0, 31); + RDHI = BITS(rst, 32, 63); + if (inst_cream->S) { + cpu->NFlag = BIT(RDHI, 31); + cpu->ZFlag = (RDHI == 0 && RDLO == 0); } - - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(smlalxy_inst)); - FETCH_INST; - GOTO_NEXT_INST; } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(umlal_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - SMLAW_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; +SMLALXY_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component; + + u64 operand1 = RN; + u64 operand2 = RM; + + if (inst_cream->x != 0) + operand1 >>= 16; + if (inst_cream->y != 0) + operand2 >>= 16; + operand1 &= 0xFFFF; + if (operand1 & 0x8000) + operand1 -= 65536; + operand2 &= 0xFFFF; + if (operand2 & 0x8000) + operand2 -= 65536; + + u64 dest = ((u64)RDHI << 32 | RDLO) + (operand1 * operand2); + RDLO = (dest & 0xFFFFFFFF); + RDHI = ((dest >> 32) & 0xFFFFFFFF); + } + + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(smlalxy_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - const u32 rm_val = RM; - const u32 rn_val = RN; - const u32 ra_val = cpu->Reg[inst_cream->Ra]; - const bool high = (inst_cream->m == 1); +SMLAW_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; - const s16 operand2 = (high) ? ((rm_val >> 16) & 0xFFFF) : (rm_val & 0xFFFF); - const s64 result = (s64)(s32)rn_val * (s64)(s32)operand2 + ((s64)(s32)ra_val << 16); + const u32 rm_val = RM; + const u32 rn_val = RN; + const u32 ra_val = cpu->Reg[inst_cream->Ra]; + const bool high = (inst_cream->m == 1); - RD = BITS(result, 16, 47); + const s16 operand2 = (high) ? ((rm_val >> 16) & 0xFFFF) : (rm_val & 0xFFFF); + const s64 result = (s64)(s32)rn_val * (s64)(s32)operand2 + ((s64)(s32)ra_val << 16); - if ((result >> 16) != (s32)RD) - cpu->Cpsr |= (1 << 27); - } + RD = BITS(result, 16, 47); - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(smlad_inst)); - FETCH_INST; - GOTO_NEXT_INST; + if ((result >> 16) != (s32)RD) + cpu->Cpsr |= (1 << 27); } - SMLALD_INST: - SMLSLD_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - smlald_inst* const inst_cream = (smlald_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(smlad_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - const bool do_swap = (inst_cream->swap == 1); - const u32 rdlo_val = RDLO; - const u32 rdhi_val = RDHI; - const u32 rn_val = RN; - u32 rm_val = RM; +SMLALD_INST: +SMLSLD_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + smlald_inst* const inst_cream = (smlald_inst*)inst_base->component; - if (do_swap) - rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16)); + const bool do_swap = (inst_cream->swap == 1); + const u32 rdlo_val = RDLO; + const u32 rdhi_val = RDHI; + const u32 rn_val = RN; + u32 rm_val = RM; - const s32 product1 = (s16)(rn_val & 0xFFFF) * (s16)(rm_val & 0xFFFF); - const s32 product2 = (s16)((rn_val >> 16) & 0xFFFF) * (s16)((rm_val >> 16) & 0xFFFF); - s64 result; + if (do_swap) + rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16)); - // SMLALD - if (BIT(inst_cream->op2, 1) == 0) { - result = (product1 + product2) + (s64)(rdlo_val | ((s64)rdhi_val << 32)); - } - // SMLSLD - else { - result = (product1 - product2) + (s64)(rdlo_val | ((s64)rdhi_val << 32)); - } + const s32 product1 = (s16)(rn_val & 0xFFFF) * (s16)(rm_val & 0xFFFF); + const s32 product2 = (s16)((rn_val >> 16) & 0xFFFF) * (s16)((rm_val >> 16) & 0xFFFF); + s64 result; - RDLO = (result & 0xFFFFFFFF); - RDHI = ((result >> 32) & 0xFFFFFFFF); + // SMLALD + if (BIT(inst_cream->op2, 1) == 0) { + result = (product1 + product2) + (s64)(rdlo_val | ((s64)rdhi_val << 32)); + } + // SMLSLD + else { + result = (product1 - product2) + (s64)(rdlo_val | ((s64)rdhi_val << 32)); } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(smlald_inst)); - FETCH_INST; - GOTO_NEXT_INST; + RDLO = (result & 0xFFFFFFFF); + RDHI = ((result >> 32) & 0xFFFFFFFF); } - SMMLA_INST: - SMMLS_INST: - SMMUL_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; - - const u32 rm_val = RM; - const u32 rn_val = RN; - const bool do_round = (inst_cream->m == 1); + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(smlald_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - // Assume SMMUL by default. - s64 result = (s64)(s32)rn_val * (s64)(s32)rm_val; +SMMLA_INST: +SMMLS_INST: +SMMUL_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; - if (inst_cream->Ra != 15) { - const u32 ra_val = cpu->Reg[inst_cream->Ra]; + const u32 rm_val = RM; + const u32 rn_val = RN; + const bool do_round = (inst_cream->m == 1); - // SMMLA, otherwise SMMLS - if (BIT(inst_cream->op2, 1) == 0) - result += ((s64)ra_val << 32); - else - result = ((s64)ra_val << 32) - result; - } + // Assume SMMUL by default. + s64 result = (s64)(s32)rn_val * (s64)(s32)rm_val; - if (do_round) - result += 0x80000000; + if (inst_cream->Ra != 15) { + const u32 ra_val = cpu->Reg[inst_cream->Ra]; - RD = ((result >> 32) & 0xFFFFFFFF); + // SMMLA, otherwise SMMLS + if (BIT(inst_cream->op2, 1) == 0) + result += ((s64)ra_val << 32); + else + result = ((s64)ra_val << 32) - result; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(smlad_inst)); - FETCH_INST; - GOTO_NEXT_INST; + if (do_round) + result += 0x80000000; + + RD = ((result >> 32) & 0xFFFFFFFF); } - SMUL_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - smul_inst* inst_cream = (smul_inst*)inst_base->component; - u32 operand1, operand2; - if (inst_cream->x == 0) - operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15); - else - operand1 = (BIT(RM, 31)) ? (BITS(RM, 16, 31) | 0xffff0000) : BITS(RM, 16, 31); + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(smlad_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - if (inst_cream->y == 0) - operand2 = (BIT(RS, 15)) ? (BITS(RS, 0, 15) | 0xffff0000) : BITS(RS, 0, 15); - else - operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31); - RD = operand1 * operand2; +SMUL_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + smul_inst* inst_cream = (smul_inst*)inst_base->component; + u32 operand1, operand2; + if (inst_cream->x == 0) + operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15); + else + operand1 = (BIT(RM, 31)) ? (BITS(RM, 16, 31) | 0xffff0000) : BITS(RM, 16, 31); + + if (inst_cream->y == 0) + operand2 = (BIT(RS, 15)) ? (BITS(RS, 0, 15) | 0xffff0000) : BITS(RS, 0, 15); + else + operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31); + RD = operand1 * operand2; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(smul_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +SMULL_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + umull_inst* inst_cream = (umull_inst*)inst_base->component; + s64 rm = RM; + s64 rs = RS; + if (BIT(rm, 31)) { + rm |= 0xffffffff00000000LL; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(smul_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - SMULL_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - umull_inst* inst_cream = (umull_inst*)inst_base->component; - s64 rm = RM; - s64 rs = RS; - if (BIT(rm, 31)) { - rm |= 0xffffffff00000000LL; - } - if (BIT(rs, 31)) { - rs |= 0xffffffff00000000LL; - } - s64 rst = rm * rs; - RDHI = BITS(rst, 32, 63); - RDLO = BITS(rst, 0, 31); + if (BIT(rs, 31)) { + rs |= 0xffffffff00000000LL; + } + s64 rst = rm * rs; + RDHI = BITS(rst, 32, 63); + RDLO = BITS(rst, 0, 31); - if (inst_cream->S) { - cpu->NFlag = BIT(RDHI, 31); - cpu->ZFlag = (RDHI == 0 && RDLO == 0); - } + if (inst_cream->S) { + cpu->NFlag = BIT(RDHI, 31); + cpu->ZFlag = (RDHI == 0 && RDLO == 0); } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(umull_inst)); - FETCH_INST; - GOTO_NEXT_INST; } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(umull_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - SMULW_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; +SMULW_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; - s16 rm = (inst_cream->m == 1) ? ((RM >> 16) & 0xFFFF) : (RM & 0xFFFF); + s16 rm = (inst_cream->m == 1) ? ((RM >> 16) & 0xFFFF) : (RM & 0xFFFF); - s64 result = (s64)rm * (s64)(s32)RN; - RD = BITS(result, 16, 47); - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(smlad_inst)); - FETCH_INST; - GOTO_NEXT_INST; + s64 result = (s64)rm * (s64)(s32)RN; + RD = BITS(result, 16, 47); } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(smlad_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - SRS_INST: - { - // SRS is unconditional - ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; +SRS_INST : { + // SRS is unconditional + ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; - u32 address = 0; - inst_cream->get_addr(cpu, inst_cream->inst, address); + u32 address = 0; + inst_cream->get_addr(cpu, inst_cream->inst, address); - cpu->WriteMemory32(address + 0, cpu->Reg[14]); - cpu->WriteMemory32(address + 4, cpu->Spsr_copy); + cpu->WriteMemory32(address + 0, cpu->Reg[14]); + cpu->WriteMemory32(address + 4, cpu->Spsr_copy); - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - - SSAT_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - u8 shift_type = inst_cream->shift_type; - u8 shift_amount = inst_cream->imm5; - u32 rn_val = RN; +SSAT_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; - // 32-bit ASR is encoded as an amount of 0. - if (shift_type == 1 && shift_amount == 0) - shift_amount = 31; + u8 shift_type = inst_cream->shift_type; + u8 shift_amount = inst_cream->imm5; + u32 rn_val = RN; - if (shift_type == 0) - rn_val <<= shift_amount; - else if (shift_type == 1) - rn_val = ((s32)rn_val >> shift_amount); + // 32-bit ASR is encoded as an amount of 0. + if (shift_type == 1 && shift_amount == 0) + shift_amount = 31; - bool saturated = false; - rn_val = ARMul_SignedSatQ(rn_val, inst_cream->sat_imm, &saturated); + if (shift_type == 0) + rn_val <<= shift_amount; + else if (shift_type == 1) + rn_val = ((s32)rn_val >> shift_amount); - if (saturated) - cpu->Cpsr |= (1 << 27); + bool saturated = false; + rn_val = ARMul_SignedSatQ(rn_val, inst_cream->sat_imm, &saturated); - RD = rn_val; - } + if (saturated) + cpu->Cpsr |= (1 << 27); - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ssat_inst)); - FETCH_INST; - GOTO_NEXT_INST; + RD = rn_val; } - SSAT16_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; - const u8 saturate_to = inst_cream->sat_imm; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ssat_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - bool sat1 = false; - bool sat2 = false; +SSAT16_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; + const u8 saturate_to = inst_cream->sat_imm; - RD = (ARMul_SignedSatQ((s16)RN, saturate_to, &sat1) & 0xFFFF) | - ARMul_SignedSatQ((s32)RN >> 16, saturate_to, &sat2) << 16; + bool sat1 = false; + bool sat2 = false; - if (sat1 || sat2) - cpu->Cpsr |= (1 << 27); - } + RD = (ARMul_SignedSatQ((s16)RN, saturate_to, &sat1) & 0xFFFF) | + ARMul_SignedSatQ((s32)RN >> 16, saturate_to, &sat2) << 16; - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ssat_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - - STC_INST: - { - // Instruction not implemented - //LOG_CRITICAL(Core_ARM11, "unimplemented instruction"); - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(stc_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - STM_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ldst_inst* inst_cream = (ldst_inst*)inst_base->component; - unsigned int inst = inst_cream->inst; - - unsigned int Rn = BITS(inst, 16, 19); - unsigned int old_RN = cpu->Reg[Rn]; - - inst_cream->get_addr(cpu, inst_cream->inst, addr); - if (BIT(inst_cream->inst, 22) == 1) { - for (int i = 0; i < 13; i++) { - if (BIT(inst_cream->inst, i)) { - cpu->WriteMemory32(addr, cpu->Reg[i]); - addr += 4; - } - } - if (BIT(inst_cream->inst, 13)) { - if (cpu->Mode == USER32MODE) - cpu->WriteMemory32(addr, cpu->Reg[13]); - else - cpu->WriteMemory32(addr, cpu->Reg_usr[0]); + if (sat1 || sat2) + cpu->Cpsr |= (1 << 27); + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ssat_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} + +STC_INST : { + // Instruction not implemented + // LOG_CRITICAL(Core_ARM11, "unimplemented instruction"); + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(stc_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +STM_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + unsigned int inst = inst_cream->inst; + + unsigned int Rn = BITS(inst, 16, 19); + unsigned int old_RN = cpu->Reg[Rn]; + + inst_cream->get_addr(cpu, inst_cream->inst, addr); + if (BIT(inst_cream->inst, 22) == 1) { + for (int i = 0; i < 13; i++) { + if (BIT(inst_cream->inst, i)) { + cpu->WriteMemory32(addr, cpu->Reg[i]); addr += 4; } - if (BIT(inst_cream->inst, 14)) { - if (cpu->Mode == USER32MODE) - cpu->WriteMemory32(addr, cpu->Reg[14]); + } + if (BIT(inst_cream->inst, 13)) { + if (cpu->Mode == USER32MODE) + cpu->WriteMemory32(addr, cpu->Reg[13]); + else + cpu->WriteMemory32(addr, cpu->Reg_usr[0]); + + addr += 4; + } + if (BIT(inst_cream->inst, 14)) { + if (cpu->Mode == USER32MODE) + cpu->WriteMemory32(addr, cpu->Reg[14]); + else + cpu->WriteMemory32(addr, cpu->Reg_usr[1]); + + addr += 4; + } + if (BIT(inst_cream->inst, 15)) { + cpu->WriteMemory32(addr, cpu->Reg[15] + 8); + } + } else { + for (int i = 0; i < 15; i++) { + if (BIT(inst_cream->inst, i)) { + if (i == Rn) + cpu->WriteMemory32(addr, old_RN); else - cpu->WriteMemory32(addr, cpu->Reg_usr[1]); + cpu->WriteMemory32(addr, cpu->Reg[i]); addr += 4; } - if (BIT(inst_cream->inst, 15)) { - cpu->WriteMemory32(addr, cpu->Reg[15] + 8); - } - } else { - for (int i = 0; i < 15; i++) { - if (BIT(inst_cream->inst, i)) { - if (i == Rn) - cpu->WriteMemory32(addr, old_RN); - else - cpu->WriteMemory32(addr, cpu->Reg[i]); - - addr += 4; - } - } + } - // Check PC reg - if (BIT(inst_cream->inst, 15)) { - cpu->WriteMemory32(addr, cpu->Reg[15] + 8); - } + // Check PC reg + if (BIT(inst_cream->inst, 15)) { + cpu->WriteMemory32(addr, cpu->Reg[15] + 8); } } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; } - SXTB_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - sxtb_inst* inst_cream = (sxtb_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +SXTB_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + sxtb_inst* inst_cream = (sxtb_inst*)inst_base->component; - unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate); - if (BIT(operand2, 7)) { - operand2 |= 0xffffff00; - } else { - operand2 &= 0xff; - } - RD = operand2; + unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate); + if (BIT(operand2, 7)) { + operand2 |= 0xffffff00; + } else { + operand2 &= 0xff; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(sxtb_inst)); - FETCH_INST; - GOTO_NEXT_INST; + RD = operand2; } - STR_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ldst_inst* inst_cream = (ldst_inst*)inst_base->component; - inst_cream->get_addr(cpu, inst_cream->inst, addr); + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(sxtb_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +STR_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr); - unsigned int reg = BITS(inst_cream->inst, 12, 15); - unsigned int value = cpu->Reg[reg]; + unsigned int reg = BITS(inst_cream->inst, 12, 15); + unsigned int value = cpu->Reg[reg]; - if (reg == 15) - value += 2 * cpu->GetInstructionSize(); + if (reg == 15) + value += 2 * cpu->GetInstructionSize(); - cpu->WriteMemory32(addr, value); - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - UXTB_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - uxtb_inst* inst_cream = (uxtb_inst*)inst_base->component; - RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff; - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(uxtb_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - UXTAB_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - uxtab_inst* inst_cream = (uxtab_inst*)inst_base->component; - - unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff; - RD = RN + operand2; - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(uxtab_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - STRB_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ldst_inst* inst_cream = (ldst_inst*)inst_base->component; - inst_cream->get_addr(cpu, inst_cream->inst, addr); - unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; - cpu->WriteMemory8(addr, value); - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; + cpu->WriteMemory32(addr, value); } - STRBT_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ldst_inst* inst_cream = (ldst_inst*)inst_base->component; - inst_cream->get_addr(cpu, inst_cream->inst, addr); + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +UXTB_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + uxtb_inst* inst_cream = (uxtb_inst*)inst_base->component; + RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(uxtb_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +UXTAB_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + uxtab_inst* inst_cream = (uxtab_inst*)inst_base->component; - const u32 previous_mode = cpu->Mode; - const u32 value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; + unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff; + RD = RN + operand2; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(uxtab_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +STRB_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr); + unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; + cpu->WriteMemory8(addr, value); + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +STRBT_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr); - cpu->ChangePrivilegeMode(USER32MODE); - cpu->WriteMemory8(addr, value); - cpu->ChangePrivilegeMode(previous_mode); - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - STRD_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ldst_inst* inst_cream = (ldst_inst*)inst_base->component; - inst_cream->get_addr(cpu, inst_cream->inst, addr); - - // The 3DS doesn't have the Large Physical Access Extension (LPAE) - // so STRD wouldn't store these as a single write. - cpu->WriteMemory32(addr + 0, cpu->Reg[BITS(inst_cream->inst, 12, 15)]); - cpu->WriteMemory32(addr + 4, cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1]); - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - STREX_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - unsigned int write_addr = cpu->Reg[inst_cream->Rn]; - - if (cpu->IsExclusiveMemoryAccess(write_addr)) { - cpu->UnsetExclusiveMemoryAddress(); - cpu->WriteMemory32(write_addr, RM); - RD = 0; - } else { - // Failed to write due to mutex access - RD = 1; - } - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - STREXB_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - unsigned int write_addr = cpu->Reg[inst_cream->Rn]; - - if (cpu->IsExclusiveMemoryAccess(write_addr)) { - cpu->UnsetExclusiveMemoryAddress(); - cpu->WriteMemory8(write_addr, cpu->Reg[inst_cream->Rm]); - RD = 0; - } else { - // Failed to write due to mutex access - RD = 1; - } - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - STREXD_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - unsigned int write_addr = cpu->Reg[inst_cream->Rn]; - - if (cpu->IsExclusiveMemoryAccess(write_addr)) { - cpu->UnsetExclusiveMemoryAddress(); - - const u32 rt = cpu->Reg[inst_cream->Rm + 0]; - const u32 rt2 = cpu->Reg[inst_cream->Rm + 1]; - u64 value; - - if (cpu->InBigEndianMode()) - value = (((u64)rt << 32) | rt2); - else - value = (((u64)rt2 << 32) | rt); + const u32 previous_mode = cpu->Mode; + const u32 value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; - cpu->WriteMemory64(write_addr, value); - RD = 0; - } - else { - // Failed to write due to mutex access - RD = 1; - } - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - STREXH_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - unsigned int write_addr = cpu->Reg[inst_cream->Rn]; - - if (cpu->IsExclusiveMemoryAccess(write_addr)) { - cpu->UnsetExclusiveMemoryAddress(); - cpu->WriteMemory16(write_addr, RM); - RD = 0; - } else { - // Failed to write due to mutex access - RD = 1; - } + cpu->ChangePrivilegeMode(USER32MODE); + cpu->WriteMemory8(addr, value); + cpu->ChangePrivilegeMode(previous_mode); + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +STRD_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr); + + // The 3DS doesn't have the Large Physical Access Extension (LPAE) + // so STRD wouldn't store these as a single write. + cpu->WriteMemory32(addr + 0, cpu->Reg[BITS(inst_cream->inst, 12, 15)]); + cpu->WriteMemory32(addr + 4, cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1]); + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +STREX_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int write_addr = cpu->Reg[inst_cream->Rn]; + + if (cpu->IsExclusiveMemoryAccess(write_addr)) { + cpu->UnsetExclusiveMemoryAddress(); + cpu->WriteMemory32(write_addr, RM); + RD = 0; + } else { + // Failed to write due to mutex access + RD = 1; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - STRH_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ldst_inst* inst_cream = (ldst_inst*)inst_base->component; - inst_cream->get_addr(cpu, inst_cream->inst, addr); - - unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xffff; - cpu->WriteMemory16(addr, value); + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +STREXB_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int write_addr = cpu->Reg[inst_cream->Rn]; + + if (cpu->IsExclusiveMemoryAccess(write_addr)) { + cpu->UnsetExclusiveMemoryAddress(); + cpu->WriteMemory8(write_addr, cpu->Reg[inst_cream->Rm]); + RD = 0; + } else { + // Failed to write due to mutex access + RD = 1; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; } - STRT_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ldst_inst* inst_cream = (ldst_inst*)inst_base->component; - inst_cream->get_addr(cpu, inst_cream->inst, addr); + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +STREXD_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int write_addr = cpu->Reg[inst_cream->Rn]; - const u32 previous_mode = cpu->Mode; - const u32 rt_index = BITS(inst_cream->inst, 12, 15); + if (cpu->IsExclusiveMemoryAccess(write_addr)) { + cpu->UnsetExclusiveMemoryAddress(); - u32 value = cpu->Reg[rt_index]; - if (rt_index == 15) - value += 2 * cpu->GetInstructionSize(); + const u32 rt = cpu->Reg[inst_cream->Rm + 0]; + const u32 rt2 = cpu->Reg[inst_cream->Rm + 1]; + u64 value; - cpu->ChangePrivilegeMode(USER32MODE); - cpu->WriteMemory32(addr, value); - cpu->ChangePrivilegeMode(previous_mode); + if (cpu->InBigEndianMode()) + value = (((u64)rt << 32) | rt2); + else + value = (((u64)rt2 << 32) | rt); + + cpu->WriteMemory64(write_addr, value); + RD = 0; + } else { + // Failed to write due to mutex access + RD = 1; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ldst_inst)); - FETCH_INST; - GOTO_NEXT_INST; } - SUB_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - sub_inst* const inst_cream = (sub_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +STREXH_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + unsigned int write_addr = cpu->Reg[inst_cream->Rn]; + + if (cpu->IsExclusiveMemoryAccess(write_addr)) { + cpu->UnsetExclusiveMemoryAddress(); + cpu->WriteMemory16(write_addr, RM); + RD = 0; + } else { + // Failed to write due to mutex access + RD = 1; + } + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +STRH_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr); - u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn); + unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xffff; + cpu->WriteMemory16(addr, value); + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +STRT_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + inst_cream->get_addr(cpu, inst_cream->inst, addr); - bool carry; - bool overflow; - RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow); + const u32 previous_mode = cpu->Mode; + const u32 rt_index = BITS(inst_cream->inst, 12, 15); - if (inst_cream->S && (inst_cream->Rd == 15)) { - if (CurrentModeHasSPSR) { - cpu->Cpsr = cpu->Spsr_copy; - cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); - LOAD_NZCVT; - } - } else if (inst_cream->S) { - UPDATE_NFLAG(RD); - UPDATE_ZFLAG(RD); - cpu->CFlag = carry; - cpu->VFlag = overflow; - } - if (inst_cream->Rd == 15) { - INC_PC(sizeof(sub_inst)); - goto DISPATCH; - } - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(sub_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - SWI_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - swi_inst* const inst_cream = (swi_inst*)inst_base->component; - SVC::CallSVC(inst_cream->num & 0xFFFF); - } + u32 value = cpu->Reg[rt_index]; + if (rt_index == 15) + value += 2 * cpu->GetInstructionSize(); - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(swi_inst)); - FETCH_INST; - GOTO_NEXT_INST; + cpu->ChangePrivilegeMode(USER32MODE); + cpu->WriteMemory32(addr, value); + cpu->ChangePrivilegeMode(previous_mode); } - SWP_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - swp_inst* inst_cream = (swp_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +SUB_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + sub_inst* const inst_cream = (sub_inst*)inst_base->component; - addr = RN; - unsigned int value = cpu->ReadMemory32(addr); - cpu->WriteMemory32(addr, RM); + u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn); - RD = value; + bool carry; + bool overflow; + RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow); + + if (inst_cream->S && (inst_cream->Rd == 15)) { + if (CurrentModeHasSPSR) { + cpu->Cpsr = cpu->Spsr_copy; + cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); + LOAD_NZCVT; + } + } else if (inst_cream->S) { + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(swp_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - SWPB_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - swp_inst* inst_cream = (swp_inst*)inst_base->component; - addr = RN; - unsigned int value = cpu->ReadMemory8(addr); - cpu->WriteMemory8(addr, (RM & 0xFF)); - RD = value; + if (inst_cream->Rd == 15) { + INC_PC(sizeof(sub_inst)); + goto DISPATCH; } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(swp_inst)); - FETCH_INST; - GOTO_NEXT_INST; } - SXTAB_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - sxtab_inst* inst_cream = (sxtab_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(sub_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +SWI_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + swi_inst* const inst_cream = (swi_inst*)inst_base->component; + SVC::CallSVC(inst_cream->num & 0xFFFF); + } - unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(swi_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +SWP_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + swp_inst* inst_cream = (swp_inst*)inst_base->component; - // Sign extend for byte - operand2 = (0x80 & operand2)? (0xFFFFFF00 | operand2):operand2; - RD = RN + operand2; - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(uxtab_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - - SXTAB16_INST: - SXTB16_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - sxtab_inst* const inst_cream = (sxtab_inst*)inst_base->component; - - const u8 rotation = inst_cream->rotate * 8; - u32 rm_val = RM; - u32 rn_val = RN; - - if (rotation) - rm_val = ((rm_val << (32 - rotation)) | (rm_val >> rotation)); - - // SXTB16 - if (inst_cream->Rn == 15) { - u32 lo = (u32)(s8)rm_val; - u32 hi = (u32)(s8)(rm_val >> 16); - RD = (lo | (hi << 16)); - } - // SXTAB16 - else { - u32 lo = (rn_val & 0xFFFF) + (u32)(s8)(rm_val & 0xFF); - u32 hi = ((rn_val >> 16) & 0xFFFF) + (u32)(s8)((rm_val >> 16) & 0xFF); - RD = (lo | (hi << 16)); - } - } + addr = RN; + unsigned int value = cpu->ReadMemory32(addr); + cpu->WriteMemory32(addr, RM); - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(sxtab_inst)); - FETCH_INST; - GOTO_NEXT_INST; + RD = value; } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(swp_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +SWPB_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + swp_inst* inst_cream = (swp_inst*)inst_base->component; + addr = RN; + unsigned int value = cpu->ReadMemory8(addr); + cpu->WriteMemory8(addr, (RM & 0xFF)); + RD = value; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(swp_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +SXTAB_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + sxtab_inst* inst_cream = (sxtab_inst*)inst_base->component; - SXTAH_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - sxtah_inst* inst_cream = (sxtah_inst*)inst_base->component; + unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff; - unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff; - // Sign extend for half - operand2 = (0x8000 & operand2) ? (0xFFFF0000 | operand2) : operand2; - RD = RN + operand2; - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(sxtah_inst)); - FETCH_INST; - GOTO_NEXT_INST; + // Sign extend for byte + operand2 = (0x80 & operand2) ? (0xFFFFFF00 | operand2) : operand2; + RD = RN + operand2; } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(uxtab_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - TEQ_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - teq_inst* const inst_cream = (teq_inst*)inst_base->component; - - u32 lop = RN; - u32 rop = SHIFTER_OPERAND; +SXTAB16_INST: +SXTB16_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + sxtab_inst* const inst_cream = (sxtab_inst*)inst_base->component; - if (inst_cream->Rn == 15) - lop += cpu->GetInstructionSize() * 2; + const u8 rotation = inst_cream->rotate * 8; + u32 rm_val = RM; + u32 rn_val = RN; - u32 result = lop ^ rop; + if (rotation) + rm_val = ((rm_val << (32 - rotation)) | (rm_val >> rotation)); - UPDATE_NFLAG(result); - UPDATE_ZFLAG(result); - UPDATE_CFLAG_WITH_SC; + // SXTB16 + if (inst_cream->Rn == 15) { + u32 lo = (u32)(s8)rm_val; + u32 hi = (u32)(s8)(rm_val >> 16); + RD = (lo | (hi << 16)); + } + // SXTAB16 + else { + u32 lo = (rn_val & 0xFFFF) + (u32)(s8)(rm_val & 0xFF); + u32 hi = ((rn_val >> 16) & 0xFFFF) + (u32)(s8)((rm_val >> 16) & 0xFF); + RD = (lo | (hi << 16)); } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(teq_inst)); - FETCH_INST; - GOTO_NEXT_INST; } - TST_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - tst_inst* const inst_cream = (tst_inst*)inst_base->component; - u32 lop = RN; - u32 rop = SHIFTER_OPERAND; - - if (inst_cream->Rn == 15) - lop += cpu->GetInstructionSize() * 2; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(sxtab_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - u32 result = lop & rop; +SXTAH_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + sxtah_inst* inst_cream = (sxtah_inst*)inst_base->component; - UPDATE_NFLAG(result); - UPDATE_ZFLAG(result); - UPDATE_CFLAG_WITH_SC; - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(tst_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - - UADD8_INST: - UADD16_INST: - UADDSUBX_INST: - USUB8_INST: - USUB16_INST: - USUBADDX_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; - - const u8 op2 = inst_cream->op2; - const u32 rm_val = RM; - const u32 rn_val = RN; + unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff; + // Sign extend for half + operand2 = (0x8000 & operand2) ? (0xFFFF0000 | operand2) : operand2; + RD = RN + operand2; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(sxtah_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - s32 lo_result = 0; - s32 hi_result = 0; +TEQ_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + teq_inst* const inst_cream = (teq_inst*)inst_base->component; - // UADD16 - if (op2 == 0x00) { - lo_result = (rn_val & 0xFFFF) + (rm_val & 0xFFFF); - hi_result = ((rn_val >> 16) & 0xFFFF) + ((rm_val >> 16) & 0xFFFF); - - if (lo_result & 0xFFFF0000) { - cpu->Cpsr |= (1 << 16); - cpu->Cpsr |= (1 << 17); - } else { - cpu->Cpsr &= ~(1 << 16); - cpu->Cpsr &= ~(1 << 17); - } + u32 lop = RN; + u32 rop = SHIFTER_OPERAND; - if (hi_result & 0xFFFF0000) { - cpu->Cpsr |= (1 << 18); - cpu->Cpsr |= (1 << 19); - } else { - cpu->Cpsr &= ~(1 << 18); - cpu->Cpsr &= ~(1 << 19); - } - } - // UASX - else if (op2 == 0x01) { - lo_result = (rn_val & 0xFFFF) - ((rm_val >> 16) & 0xFFFF); - hi_result = ((rn_val >> 16) & 0xFFFF) + (rm_val & 0xFFFF); - - if (lo_result >= 0) { - cpu->Cpsr |= (1 << 16); - cpu->Cpsr |= (1 << 17); - } else { - cpu->Cpsr &= ~(1 << 16); - cpu->Cpsr &= ~(1 << 17); - } + if (inst_cream->Rn == 15) + lop += cpu->GetInstructionSize() * 2; - if (hi_result >= 0x10000) { - cpu->Cpsr |= (1 << 18); - cpu->Cpsr |= (1 << 19); - } else { - cpu->Cpsr &= ~(1 << 18); - cpu->Cpsr &= ~(1 << 19); - } - } - // USAX - else if (op2 == 0x02) { - lo_result = (rn_val & 0xFFFF) + ((rm_val >> 16) & 0xFFFF); - hi_result = ((rn_val >> 16) & 0xFFFF) - (rm_val & 0xFFFF); - - if (lo_result >= 0x10000) { - cpu->Cpsr |= (1 << 16); - cpu->Cpsr |= (1 << 17); - } else { - cpu->Cpsr &= ~(1 << 16); - cpu->Cpsr &= ~(1 << 17); - } + u32 result = lop ^ rop; - if (hi_result >= 0) { - cpu->Cpsr |= (1 << 18); - cpu->Cpsr |= (1 << 19); - } else { - cpu->Cpsr &= ~(1 << 18); - cpu->Cpsr &= ~(1 << 19); - } - } - // USUB16 - else if (op2 == 0x03) { - lo_result = (rn_val & 0xFFFF) - (rm_val & 0xFFFF); - hi_result = ((rn_val >> 16) & 0xFFFF) - ((rm_val >> 16) & 0xFFFF); - - if ((lo_result & 0xFFFF0000) == 0) { - cpu->Cpsr |= (1 << 16); - cpu->Cpsr |= (1 << 17); - } else { - cpu->Cpsr &= ~(1 << 16); - cpu->Cpsr &= ~(1 << 17); - } + UPDATE_NFLAG(result); + UPDATE_ZFLAG(result); + UPDATE_CFLAG_WITH_SC; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(teq_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +TST_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + tst_inst* const inst_cream = (tst_inst*)inst_base->component; - if ((hi_result & 0xFFFF0000) == 0) { - cpu->Cpsr |= (1 << 18); - cpu->Cpsr |= (1 << 19); - } else { - cpu->Cpsr &= ~(1 << 18); - cpu->Cpsr &= ~(1 << 19); - } - } - // UADD8 - else if (op2 == 0x04) { - s16 sum1 = (rn_val & 0xFF) + (rm_val & 0xFF); - s16 sum2 = ((rn_val >> 8) & 0xFF) + ((rm_val >> 8) & 0xFF); - s16 sum3 = ((rn_val >> 16) & 0xFF) + ((rm_val >> 16) & 0xFF); - s16 sum4 = ((rn_val >> 24) & 0xFF) + ((rm_val >> 24) & 0xFF); - - if (sum1 >= 0x100) - cpu->Cpsr |= (1 << 16); - else - cpu->Cpsr &= ~(1 << 16); + u32 lop = RN; + u32 rop = SHIFTER_OPERAND; - if (sum2 >= 0x100) - cpu->Cpsr |= (1 << 17); - else - cpu->Cpsr &= ~(1 << 17); + if (inst_cream->Rn == 15) + lop += cpu->GetInstructionSize() * 2; - if (sum3 >= 0x100) - cpu->Cpsr |= (1 << 18); - else - cpu->Cpsr &= ~(1 << 18); + u32 result = lop & rop; - if (sum4 >= 0x100) - cpu->Cpsr |= (1 << 19); - else - cpu->Cpsr &= ~(1 << 19); + UPDATE_NFLAG(result); + UPDATE_ZFLAG(result); + UPDATE_CFLAG_WITH_SC; + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(tst_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - lo_result = ((sum1 & 0xFF) | (sum2 & 0xFF) << 8); - hi_result = ((sum3 & 0xFF) | (sum4 & 0xFF) << 8); +UADD8_INST: +UADD16_INST: +UADDSUBX_INST: +USUB8_INST: +USUB16_INST: +USUBADDX_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + + const u8 op2 = inst_cream->op2; + const u32 rm_val = RM; + const u32 rn_val = RN; + + s32 lo_result = 0; + s32 hi_result = 0; + + // UADD16 + if (op2 == 0x00) { + lo_result = (rn_val & 0xFFFF) + (rm_val & 0xFFFF); + hi_result = ((rn_val >> 16) & 0xFFFF) + ((rm_val >> 16) & 0xFFFF); + + if (lo_result & 0xFFFF0000) { + cpu->Cpsr |= (1 << 16); + cpu->Cpsr |= (1 << 17); + } else { + cpu->Cpsr &= ~(1 << 16); + cpu->Cpsr &= ~(1 << 17); } - // USUB8 - else if (op2 == 0x07) { - s16 diff1 = (rn_val & 0xFF) - (rm_val & 0xFF); - s16 diff2 = ((rn_val >> 8) & 0xFF) - ((rm_val >> 8) & 0xFF); - s16 diff3 = ((rn_val >> 16) & 0xFF) - ((rm_val >> 16) & 0xFF); - s16 diff4 = ((rn_val >> 24) & 0xFF) - ((rm_val >> 24) & 0xFF); - - if (diff1 >= 0) - cpu->Cpsr |= (1 << 16); - else - cpu->Cpsr &= ~(1 << 16); - if (diff2 >= 0) - cpu->Cpsr |= (1 << 17); - else - cpu->Cpsr &= ~(1 << 17); - - if (diff3 >= 0) - cpu->Cpsr |= (1 << 18); - else - cpu->Cpsr &= ~(1 << 18); - - if (diff4 >= 0) - cpu->Cpsr |= (1 << 19); - else - cpu->Cpsr &= ~(1 << 19); - - lo_result = (diff1 & 0xFF) | ((diff2 & 0xFF) << 8); - hi_result = (diff3 & 0xFF) | ((diff4 & 0xFF) << 8); + if (hi_result & 0xFFFF0000) { + cpu->Cpsr |= (1 << 18); + cpu->Cpsr |= (1 << 19); + } else { + cpu->Cpsr &= ~(1 << 18); + cpu->Cpsr &= ~(1 << 19); } - - RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16); } + // UASX + else if (op2 == 0x01) { + lo_result = (rn_val & 0xFFFF) - ((rm_val >> 16) & 0xFFFF); + hi_result = ((rn_val >> 16) & 0xFFFF) + (rm_val & 0xFFFF); + + if (lo_result >= 0) { + cpu->Cpsr |= (1 << 16); + cpu->Cpsr |= (1 << 17); + } else { + cpu->Cpsr &= ~(1 << 16); + cpu->Cpsr &= ~(1 << 17); + } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - - UHADD8_INST: - UHADD16_INST: - UHADDSUBX_INST: - UHSUBADDX_INST: - UHSUB8_INST: - UHSUB16_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; - const u32 rm_val = RM; - const u32 rn_val = RN; - const u8 op2 = inst_cream->op2; - - if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) - { - u32 lo_val = 0; - u32 hi_val = 0; - - // UHADD16 - if (op2 == 0x00) { - lo_val = (rn_val & 0xFFFF) + (rm_val & 0xFFFF); - hi_val = ((rn_val >> 16) & 0xFFFF) + ((rm_val >> 16) & 0xFFFF); - } - // UHASX - else if (op2 == 0x01) { - lo_val = (rn_val & 0xFFFF) - ((rm_val >> 16) & 0xFFFF); - hi_val = ((rn_val >> 16) & 0xFFFF) + (rm_val & 0xFFFF); - } - // UHSAX - else if (op2 == 0x02) { - lo_val = (rn_val & 0xFFFF) + ((rm_val >> 16) & 0xFFFF); - hi_val = ((rn_val >> 16) & 0xFFFF) - (rm_val & 0xFFFF); - } - // UHSUB16 - else if (op2 == 0x03) { - lo_val = (rn_val & 0xFFFF) - (rm_val & 0xFFFF); - hi_val = ((rn_val >> 16) & 0xFFFF) - ((rm_val >> 16) & 0xFFFF); - } - - lo_val >>= 1; - hi_val >>= 1; - - RD = (lo_val & 0xFFFF) | ((hi_val & 0xFFFF) << 16); + if (hi_result >= 0x10000) { + cpu->Cpsr |= (1 << 18); + cpu->Cpsr |= (1 << 19); + } else { + cpu->Cpsr &= ~(1 << 18); + cpu->Cpsr &= ~(1 << 19); + } + } + // USAX + else if (op2 == 0x02) { + lo_result = (rn_val & 0xFFFF) + ((rm_val >> 16) & 0xFFFF); + hi_result = ((rn_val >> 16) & 0xFFFF) - (rm_val & 0xFFFF); + + if (lo_result >= 0x10000) { + cpu->Cpsr |= (1 << 16); + cpu->Cpsr |= (1 << 17); + } else { + cpu->Cpsr &= ~(1 << 16); + cpu->Cpsr &= ~(1 << 17); } - else if (op2 == 0x04 || op2 == 0x07) { - u32 sum1; - u32 sum2; - u32 sum3; - u32 sum4; - - // UHADD8 - if (op2 == 0x04) { - sum1 = (rn_val & 0xFF) + (rm_val & 0xFF); - sum2 = ((rn_val >> 8) & 0xFF) + ((rm_val >> 8) & 0xFF); - sum3 = ((rn_val >> 16) & 0xFF) + ((rm_val >> 16) & 0xFF); - sum4 = ((rn_val >> 24) & 0xFF) + ((rm_val >> 24) & 0xFF); - } - // UHSUB8 - else { - sum1 = (rn_val & 0xFF) - (rm_val & 0xFF); - sum2 = ((rn_val >> 8) & 0xFF) - ((rm_val >> 8) & 0xFF); - sum3 = ((rn_val >> 16) & 0xFF) - ((rm_val >> 16) & 0xFF); - sum4 = ((rn_val >> 24) & 0xFF) - ((rm_val >> 24) & 0xFF); - } - sum1 >>= 1; - sum2 >>= 1; - sum3 >>= 1; - sum4 >>= 1; + if (hi_result >= 0) { + cpu->Cpsr |= (1 << 18); + cpu->Cpsr |= (1 << 19); + } else { + cpu->Cpsr &= ~(1 << 18); + cpu->Cpsr &= ~(1 << 19); + } + } + // USUB16 + else if (op2 == 0x03) { + lo_result = (rn_val & 0xFFFF) - (rm_val & 0xFFFF); + hi_result = ((rn_val >> 16) & 0xFFFF) - ((rm_val >> 16) & 0xFFFF); + + if ((lo_result & 0xFFFF0000) == 0) { + cpu->Cpsr |= (1 << 16); + cpu->Cpsr |= (1 << 17); + } else { + cpu->Cpsr &= ~(1 << 16); + cpu->Cpsr &= ~(1 << 17); + } - RD = (sum1 & 0xFF) | ((sum2 & 0xFF) << 8) | ((sum3 & 0xFF) << 16) | ((sum4 & 0xFF) << 24); + if ((hi_result & 0xFFFF0000) == 0) { + cpu->Cpsr |= (1 << 18); + cpu->Cpsr |= (1 << 19); + } else { + cpu->Cpsr &= ~(1 << 18); + cpu->Cpsr &= ~(1 << 19); } } + // UADD8 + else if (op2 == 0x04) { + s16 sum1 = (rn_val & 0xFF) + (rm_val & 0xFF); + s16 sum2 = ((rn_val >> 8) & 0xFF) + ((rm_val >> 8) & 0xFF); + s16 sum3 = ((rn_val >> 16) & 0xFF) + ((rm_val >> 16) & 0xFF); + s16 sum4 = ((rn_val >> 24) & 0xFF) + ((rm_val >> 24) & 0xFF); + + if (sum1 >= 0x100) + cpu->Cpsr |= (1 << 16); + else + cpu->Cpsr &= ~(1 << 16); - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } + if (sum2 >= 0x100) + cpu->Cpsr |= (1 << 17); + else + cpu->Cpsr &= ~(1 << 17); - UMAAL_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - umaal_inst* const inst_cream = (umaal_inst*)inst_base->component; - const u64 rm = RM; - const u64 rn = RN; - const u64 rd_lo = RDLO; - const u64 rd_hi = RDHI; - const u64 result = (rm * rn) + rd_lo + rd_hi; + if (sum3 >= 0x100) + cpu->Cpsr |= (1 << 18); + else + cpu->Cpsr &= ~(1 << 18); - RDLO = (result & 0xFFFFFFFF); - RDHI = ((result >> 32) & 0xFFFFFFFF); - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(umaal_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - UMLAL_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - umlal_inst* inst_cream = (umlal_inst*)inst_base->component; - unsigned long long int rm = RM; - unsigned long long int rs = RS; - unsigned long long int rst = rm * rs; - unsigned long long int add = ((unsigned long long) RDHI)<<32; - add += RDLO; - rst += add; - RDLO = BITS(rst, 0, 31); - RDHI = BITS(rst, 32, 63); - - if (inst_cream->S) { - cpu->NFlag = BIT(RDHI, 31); - cpu->ZFlag = (RDHI == 0 && RDLO == 0); - } - } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(umlal_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - UMULL_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - umull_inst* inst_cream = (umull_inst*)inst_base->component; - unsigned long long int rm = RM; - unsigned long long int rs = RS; - unsigned long long int rst = rm * rs; - RDHI = BITS(rst, 32, 63); - RDLO = BITS(rst, 0, 31); - - if (inst_cream->S) { - cpu->NFlag = BIT(RDHI, 31); - cpu->ZFlag = (RDHI == 0 && RDLO == 0); - } + if (sum4 >= 0x100) + cpu->Cpsr |= (1 << 19); + else + cpu->Cpsr &= ~(1 << 19); + + lo_result = ((sum1 & 0xFF) | (sum2 & 0xFF) << 8); + hi_result = ((sum3 & 0xFF) | (sum4 & 0xFF) << 8); } - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(umull_inst)); - FETCH_INST; - GOTO_NEXT_INST; - } - B_2_THUMB: - { - b_2_thumb* inst_cream = (b_2_thumb*)inst_base->component; - cpu->Reg[15] = cpu->Reg[15] + 4 + inst_cream->imm; - INC_PC(sizeof(b_2_thumb)); - goto DISPATCH; - } - B_COND_THUMB: - { - b_cond_thumb* inst_cream = (b_cond_thumb*)inst_base->component; + // USUB8 + else if (op2 == 0x07) { + s16 diff1 = (rn_val & 0xFF) - (rm_val & 0xFF); + s16 diff2 = ((rn_val >> 8) & 0xFF) - ((rm_val >> 8) & 0xFF); + s16 diff3 = ((rn_val >> 16) & 0xFF) - ((rm_val >> 16) & 0xFF); + s16 diff4 = ((rn_val >> 24) & 0xFF) - ((rm_val >> 24) & 0xFF); + + if (diff1 >= 0) + cpu->Cpsr |= (1 << 16); + else + cpu->Cpsr &= ~(1 << 16); - if(CondPassed(cpu, inst_cream->cond)) - cpu->Reg[15] = cpu->Reg[15] + 4 + inst_cream->imm; - else - cpu->Reg[15] += 2; + if (diff2 >= 0) + cpu->Cpsr |= (1 << 17); + else + cpu->Cpsr &= ~(1 << 17); - INC_PC(sizeof(b_cond_thumb)); - goto DISPATCH; - } - BL_1_THUMB: - { - bl_1_thumb* inst_cream = (bl_1_thumb*)inst_base->component; - cpu->Reg[14] = cpu->Reg[15] + 4 + inst_cream->imm; - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(bl_1_thumb)); - FETCH_INST; - GOTO_NEXT_INST; - } - BL_2_THUMB: - { - bl_2_thumb* inst_cream = (bl_2_thumb*)inst_base->component; - int tmp = ((cpu->Reg[15] + 2) | 1); - cpu->Reg[15] = (cpu->Reg[14] + inst_cream->imm); - cpu->Reg[14] = tmp; - INC_PC(sizeof(bl_2_thumb)); - goto DISPATCH; - } - BLX_1_THUMB: - { - // BLX 1 for armv5t and above - u32 tmp = cpu->Reg[15]; - blx_1_thumb* inst_cream = (blx_1_thumb*)inst_base->component; - cpu->Reg[15] = (cpu->Reg[14] + inst_cream->imm) & 0xFFFFFFFC; - cpu->Reg[14] = ((tmp + 2) | 1); - cpu->TFlag = 0; - INC_PC(sizeof(blx_1_thumb)); - goto DISPATCH; - } + if (diff3 >= 0) + cpu->Cpsr |= (1 << 18); + else + cpu->Cpsr &= ~(1 << 18); - UQADD8_INST: - UQADD16_INST: - UQADDSUBX_INST: - UQSUB8_INST: - UQSUB16_INST: - UQSUBADDX_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + if (diff4 >= 0) + cpu->Cpsr |= (1 << 19); + else + cpu->Cpsr &= ~(1 << 19); - const u8 op2 = inst_cream->op2; - const u32 rm_val = RM; - const u32 rn_val = RN; + lo_result = (diff1 & 0xFF) | ((diff2 & 0xFF) << 8); + hi_result = (diff3 & 0xFF) | ((diff4 & 0xFF) << 8); + } - u16 lo_val = 0; - u16 hi_val = 0; + RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16); + } - // UQADD16 + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} + +UHADD8_INST: +UHADD16_INST: +UHADDSUBX_INST: +UHSUBADDX_INST: +UHSUB8_INST: +UHSUB16_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + const u32 rm_val = RM; + const u32 rn_val = RN; + const u8 op2 = inst_cream->op2; + + if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) { + u32 lo_val = 0; + u32 hi_val = 0; + + // UHADD16 if (op2 == 0x00) { - lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, rm_val & 0xFFFF); - hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF); + lo_val = (rn_val & 0xFFFF) + (rm_val & 0xFFFF); + hi_val = ((rn_val >> 16) & 0xFFFF) + ((rm_val >> 16) & 0xFFFF); } - // UQASX + // UHASX else if (op2 == 0x01) { - lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF); - hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF); + lo_val = (rn_val & 0xFFFF) - ((rm_val >> 16) & 0xFFFF); + hi_val = ((rn_val >> 16) & 0xFFFF) + (rm_val & 0xFFFF); } - // UQSAX + // UHSAX else if (op2 == 0x02) { - lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF); - hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF); + lo_val = (rn_val & 0xFFFF) + ((rm_val >> 16) & 0xFFFF); + hi_val = ((rn_val >> 16) & 0xFFFF) - (rm_val & 0xFFFF); } - // UQSUB16 + // UHSUB16 else if (op2 == 0x03) { - lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, rm_val & 0xFFFF); - hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF); + lo_val = (rn_val & 0xFFFF) - (rm_val & 0xFFFF); + hi_val = ((rn_val >> 16) & 0xFFFF) - ((rm_val >> 16) & 0xFFFF); } - // UQADD8 - else if (op2 == 0x04) { - lo_val = ARMul_UnsignedSaturatedAdd8(rn_val, rm_val) | - ARMul_UnsignedSaturatedAdd8(rn_val >> 8, rm_val >> 8) << 8; - hi_val = ARMul_UnsignedSaturatedAdd8(rn_val >> 16, rm_val >> 16) | - ARMul_UnsignedSaturatedAdd8(rn_val >> 24, rm_val >> 24) << 8; + + lo_val >>= 1; + hi_val >>= 1; + + RD = (lo_val & 0xFFFF) | ((hi_val & 0xFFFF) << 16); + } else if (op2 == 0x04 || op2 == 0x07) { + u32 sum1; + u32 sum2; + u32 sum3; + u32 sum4; + + // UHADD8 + if (op2 == 0x04) { + sum1 = (rn_val & 0xFF) + (rm_val & 0xFF); + sum2 = ((rn_val >> 8) & 0xFF) + ((rm_val >> 8) & 0xFF); + sum3 = ((rn_val >> 16) & 0xFF) + ((rm_val >> 16) & 0xFF); + sum4 = ((rn_val >> 24) & 0xFF) + ((rm_val >> 24) & 0xFF); } - // UQSUB8 + // UHSUB8 else { - lo_val = ARMul_UnsignedSaturatedSub8(rn_val, rm_val) | - ARMul_UnsignedSaturatedSub8(rn_val >> 8, rm_val >> 8) << 8; - hi_val = ARMul_UnsignedSaturatedSub8(rn_val >> 16, rm_val >> 16) | - ARMul_UnsignedSaturatedSub8(rn_val >> 24, rm_val >> 24) << 8; + sum1 = (rn_val & 0xFF) - (rm_val & 0xFF); + sum2 = ((rn_val >> 8) & 0xFF) - ((rm_val >> 8) & 0xFF); + sum3 = ((rn_val >> 16) & 0xFF) - ((rm_val >> 16) & 0xFF); + sum4 = ((rn_val >> 24) & 0xFF) - ((rm_val >> 24) & 0xFF); } - RD = ((lo_val & 0xFFFF) | hi_val << 16); + sum1 >>= 1; + sum2 >>= 1; + sum3 >>= 1; + sum4 >>= 1; + + RD = (sum1 & 0xFF) | ((sum2 & 0xFF) << 8) | ((sum3 & 0xFF) << 16) | + ((sum4 & 0xFF) << 24); } + } + + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; +UMAAL_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + umaal_inst* const inst_cream = (umaal_inst*)inst_base->component; + const u64 rm = RM; + const u64 rn = RN; + const u64 rd_lo = RDLO; + const u64 rd_hi = RDHI; + const u64 result = (rm * rn) + rd_lo + rd_hi; + + RDLO = (result & 0xFFFFFFFF); + RDHI = ((result >> 32) & 0xFFFFFFFF); + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(umaal_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +UMLAL_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + umlal_inst* inst_cream = (umlal_inst*)inst_base->component; + unsigned long long int rm = RM; + unsigned long long int rs = RS; + unsigned long long int rst = rm * rs; + unsigned long long int add = ((unsigned long long)RDHI) << 32; + add += RDLO; + rst += add; + RDLO = BITS(rst, 0, 31); + RDHI = BITS(rst, 32, 63); + + if (inst_cream->S) { + cpu->NFlag = BIT(RDHI, 31); + cpu->ZFlag = (RDHI == 0 && RDLO == 0); + } + } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(umlal_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +UMULL_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + umull_inst* inst_cream = (umull_inst*)inst_base->component; + unsigned long long int rm = RM; + unsigned long long int rs = RS; + unsigned long long int rst = rm * rs; + RDHI = BITS(rst, 32, 63); + RDLO = BITS(rst, 0, 31); + + if (inst_cream->S) { + cpu->NFlag = BIT(RDHI, 31); + cpu->ZFlag = (RDHI == 0 && RDLO == 0); + } } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(umull_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} +B_2_THUMB : { + b_2_thumb* inst_cream = (b_2_thumb*)inst_base->component; + cpu->Reg[15] = cpu->Reg[15] + 4 + inst_cream->imm; + INC_PC(sizeof(b_2_thumb)); + goto DISPATCH; +} +B_COND_THUMB : { + b_cond_thumb* inst_cream = (b_cond_thumb*)inst_base->component; - USAD8_INST: - USADA8_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; + if (CondPassed(cpu, inst_cream->cond)) + cpu->Reg[15] = cpu->Reg[15] + 4 + inst_cream->imm; + else + cpu->Reg[15] += 2; - const u8 ra_idx = inst_cream->Ra; - const u32 rm_val = RM; - const u32 rn_val = RN; + INC_PC(sizeof(b_cond_thumb)); + goto DISPATCH; +} +BL_1_THUMB : { + bl_1_thumb* inst_cream = (bl_1_thumb*)inst_base->component; + cpu->Reg[14] = cpu->Reg[15] + 4 + inst_cream->imm; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(bl_1_thumb)); + FETCH_INST; + GOTO_NEXT_INST; +} +BL_2_THUMB : { + bl_2_thumb* inst_cream = (bl_2_thumb*)inst_base->component; + int tmp = ((cpu->Reg[15] + 2) | 1); + cpu->Reg[15] = (cpu->Reg[14] + inst_cream->imm); + cpu->Reg[14] = tmp; + INC_PC(sizeof(bl_2_thumb)); + goto DISPATCH; +} +BLX_1_THUMB : { + // BLX 1 for armv5t and above + u32 tmp = cpu->Reg[15]; + blx_1_thumb* inst_cream = (blx_1_thumb*)inst_base->component; + cpu->Reg[15] = (cpu->Reg[14] + inst_cream->imm) & 0xFFFFFFFC; + cpu->Reg[14] = ((tmp + 2) | 1); + cpu->TFlag = 0; + INC_PC(sizeof(blx_1_thumb)); + goto DISPATCH; +} - const u8 diff1 = ARMul_UnsignedAbsoluteDifference(rn_val & 0xFF, rm_val & 0xFF); - const u8 diff2 = ARMul_UnsignedAbsoluteDifference((rn_val >> 8) & 0xFF, (rm_val >> 8) & 0xFF); - const u8 diff3 = ARMul_UnsignedAbsoluteDifference((rn_val >> 16) & 0xFF, (rm_val >> 16) & 0xFF); - const u8 diff4 = ARMul_UnsignedAbsoluteDifference((rn_val >> 24) & 0xFF, (rm_val >> 24) & 0xFF); +UQADD8_INST: +UQADD16_INST: +UQADDSUBX_INST: +UQSUB8_INST: +UQSUB16_INST: +UQSUBADDX_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; + + const u8 op2 = inst_cream->op2; + const u32 rm_val = RM; + const u32 rn_val = RN; + + u16 lo_val = 0; + u16 hi_val = 0; + + // UQADD16 + if (op2 == 0x00) { + lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, rm_val & 0xFFFF); + hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF); + } + // UQASX + else if (op2 == 0x01) { + lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF); + hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF); + } + // UQSAX + else if (op2 == 0x02) { + lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF); + hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF); + } + // UQSUB16 + else if (op2 == 0x03) { + lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, rm_val & 0xFFFF); + hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF); + } + // UQADD8 + else if (op2 == 0x04) { + lo_val = ARMul_UnsignedSaturatedAdd8(rn_val, rm_val) | + ARMul_UnsignedSaturatedAdd8(rn_val >> 8, rm_val >> 8) << 8; + hi_val = ARMul_UnsignedSaturatedAdd8(rn_val >> 16, rm_val >> 16) | + ARMul_UnsignedSaturatedAdd8(rn_val >> 24, rm_val >> 24) << 8; + } + // UQSUB8 + else { + lo_val = ARMul_UnsignedSaturatedSub8(rn_val, rm_val) | + ARMul_UnsignedSaturatedSub8(rn_val >> 8, rm_val >> 8) << 8; + hi_val = ARMul_UnsignedSaturatedSub8(rn_val >> 16, rm_val >> 16) | + ARMul_UnsignedSaturatedSub8(rn_val >> 24, rm_val >> 24) << 8; + } + + RD = ((lo_val & 0xFFFF) | hi_val << 16); + } - u32 finalDif = (diff1 + diff2 + diff3 + diff4); + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - // Op is USADA8 if true. - if (ra_idx != 15) - finalDif += cpu->Reg[ra_idx]; +USAD8_INST: +USADA8_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - RD = finalDif; - } + const u8 ra_idx = inst_cream->Ra; + const u32 rm_val = RM; + const u32 rn_val = RN; + + const u8 diff1 = ARMul_UnsignedAbsoluteDifference(rn_val & 0xFF, rm_val & 0xFF); + const u8 diff2 = + ARMul_UnsignedAbsoluteDifference((rn_val >> 8) & 0xFF, (rm_val >> 8) & 0xFF); + const u8 diff3 = + ARMul_UnsignedAbsoluteDifference((rn_val >> 16) & 0xFF, (rm_val >> 16) & 0xFF); + const u8 diff4 = + ARMul_UnsignedAbsoluteDifference((rn_val >> 24) & 0xFF, (rm_val >> 24) & 0xFF); - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(generic_arm_inst)); - FETCH_INST; - GOTO_NEXT_INST; + u32 finalDif = (diff1 + diff2 + diff3 + diff4); + + // Op is USADA8 if true. + if (ra_idx != 15) + finalDif += cpu->Reg[ra_idx]; + + RD = finalDif; } - USAT_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(generic_arm_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - u8 shift_type = inst_cream->shift_type; - u8 shift_amount = inst_cream->imm5; - u32 rn_val = RN; +USAT_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; - // 32-bit ASR is encoded as an amount of 0. - if (shift_type == 1 && shift_amount == 0) - shift_amount = 31; + u8 shift_type = inst_cream->shift_type; + u8 shift_amount = inst_cream->imm5; + u32 rn_val = RN; - if (shift_type == 0) - rn_val <<= shift_amount; - else if (shift_type == 1) - rn_val = ((s32)rn_val >> shift_amount); + // 32-bit ASR is encoded as an amount of 0. + if (shift_type == 1 && shift_amount == 0) + shift_amount = 31; - bool saturated = false; - rn_val = ARMul_UnsignedSatQ(rn_val, inst_cream->sat_imm, &saturated); + if (shift_type == 0) + rn_val <<= shift_amount; + else if (shift_type == 1) + rn_val = ((s32)rn_val >> shift_amount); - if (saturated) - cpu->Cpsr |= (1 << 27); + bool saturated = false; + rn_val = ARMul_UnsignedSatQ(rn_val, inst_cream->sat_imm, &saturated); - RD = rn_val; - } + if (saturated) + cpu->Cpsr |= (1 << 27); - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ssat_inst)); - FETCH_INST; - GOTO_NEXT_INST; + RD = rn_val; } - USAT16_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; - const u8 saturate_to = inst_cream->sat_imm; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ssat_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - bool sat1 = false; - bool sat2 = false; +USAT16_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; + const u8 saturate_to = inst_cream->sat_imm; - RD = (ARMul_UnsignedSatQ((s16)RN, saturate_to, &sat1) & 0xFFFF) | - ARMul_UnsignedSatQ((s32)RN >> 16, saturate_to, &sat2) << 16; + bool sat1 = false; + bool sat2 = false; - if (sat1 || sat2) - cpu->Cpsr |= (1 << 27); - } + RD = (ARMul_UnsignedSatQ((s16)RN, saturate_to, &sat1) & 0xFFFF) | + ARMul_UnsignedSatQ((s32)RN >> 16, saturate_to, &sat2) << 16; - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(ssat_inst)); - FETCH_INST; - GOTO_NEXT_INST; + if (sat1 || sat2) + cpu->Cpsr |= (1 << 27); } - UXTAB16_INST: - UXTB16_INST: - { - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - uxtab_inst* const inst_cream = (uxtab_inst*)inst_base->component; + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(ssat_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - const u8 rn_idx = inst_cream->Rn; - const u32 rm_val = RM; - const u32 rotation = inst_cream->rotate * 8; - const u32 rotated_rm = ((rm_val << (32 - rotation)) | (rm_val >> rotation)); +UXTAB16_INST: +UXTB16_INST : { + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + uxtab_inst* const inst_cream = (uxtab_inst*)inst_base->component; - // UXTB16, otherwise UXTAB16 - if (rn_idx == 15) { - RD = rotated_rm & 0x00FF00FF; - } else { - const u32 rn_val = RN; - const u8 lo_rotated = (rotated_rm & 0xFF); - const u16 lo_result = (rn_val & 0xFFFF) + (u16)lo_rotated; - const u8 hi_rotated = (rotated_rm >> 16) & 0xFF; - const u16 hi_result = (rn_val >> 16) + (u16)hi_rotated; + const u8 rn_idx = inst_cream->Rn; + const u32 rm_val = RM; + const u32 rotation = inst_cream->rotate * 8; + const u32 rotated_rm = ((rm_val << (32 - rotation)) | (rm_val >> rotation)); - RD = ((hi_result << 16) | (lo_result & 0xFFFF)); - } - } + // UXTB16, otherwise UXTAB16 + if (rn_idx == 15) { + RD = rotated_rm & 0x00FF00FF; + } else { + const u32 rn_val = RN; + const u8 lo_rotated = (rotated_rm & 0xFF); + const u16 lo_result = (rn_val & 0xFFFF) + (u16)lo_rotated; + const u8 hi_rotated = (rotated_rm >> 16) & 0xFF; + const u16 hi_result = (rn_val >> 16) + (u16)hi_rotated; - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC(sizeof(uxtab_inst)); - FETCH_INST; - GOTO_NEXT_INST; + RD = ((hi_result << 16) | (lo_result & 0xFFFF)); + } } - WFE_INST: - { - // Stubbed, as WFE is a hint instruction. - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - LOG_TRACE(Core_ARM11, "WFE executed."); - } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC(sizeof(uxtab_inst)); + FETCH_INST; + GOTO_NEXT_INST; +} - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC_STUB; - FETCH_INST; - GOTO_NEXT_INST; +WFE_INST : { + // Stubbed, as WFE is a hint instruction. + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + LOG_TRACE(Core_ARM11, "WFE executed."); } - WFI_INST: - { - // Stubbed, as WFI is a hint instruction. - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - LOG_TRACE(Core_ARM11, "WFI executed."); - } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC_STUB; + FETCH_INST; + GOTO_NEXT_INST; +} - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC_STUB; - FETCH_INST; - GOTO_NEXT_INST; +WFI_INST : { + // Stubbed, as WFI is a hint instruction. + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + LOG_TRACE(Core_ARM11, "WFI executed."); } - YIELD_INST: - { - // Stubbed, as YIELD is a hint instruction. - if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { - LOG_TRACE(Core_ARM11, "YIELD executed."); - } + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC_STUB; + FETCH_INST; + GOTO_NEXT_INST; +} - cpu->Reg[15] += cpu->GetInstructionSize(); - INC_PC_STUB; - FETCH_INST; - GOTO_NEXT_INST; +YIELD_INST : { + // Stubbed, as YIELD is a hint instruction. + if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { + LOG_TRACE(Core_ARM11, "YIELD executed."); } - #define VFP_INTERPRETER_IMPL - #include "core/arm/skyeye_common/vfp/vfpinstr.cpp" - #undef VFP_INTERPRETER_IMPL + cpu->Reg[15] += cpu->GetInstructionSize(); + INC_PC_STUB; + FETCH_INST; + GOTO_NEXT_INST; +} - END: - { - SAVE_NZCVT; - cpu->NumInstrsToExecute = 0; - return num_instrs; - } - INIT_INST_LENGTH: - { - cpu->NumInstrsToExecute = 0; - return num_instrs; - } +#define VFP_INTERPRETER_IMPL +#include "core/arm/skyeye_common/vfp/vfpinstr.cpp" +#undef VFP_INTERPRETER_IMPL + +END : { + SAVE_NZCVT; + cpu->NumInstrsToExecute = 0; + return num_instrs; +} +INIT_INST_LENGTH : { + cpu->NumInstrsToExecute = 0; + return num_instrs; +} } diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp index 3576370d1..2a3dd0f53 100644 --- a/src/core/arm/dyncom/arm_dyncom_thumb.cpp +++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp @@ -21,50 +21,48 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3 *ainstr = 0xDEADC0DE; // Debugging to catch non updates switch ((tinstr & 0xF800) >> 11) { - case 0: // LSL - case 1: // LSR - case 2: // ASR - *ainstr = 0xE1B00000 // base opcode - | ((tinstr & 0x1800) >> (11 - 5)) // shift type - |((tinstr & 0x07C0) << (7 - 6)) // imm5 - |((tinstr & 0x0038) >> 3) // Rs - |((tinstr & 0x0007) << 12); // Rd + case 0: // LSL + case 1: // LSR + case 2: // ASR + *ainstr = 0xE1B00000 // base opcode + | ((tinstr & 0x1800) >> (11 - 5)) // shift type + | ((tinstr & 0x07C0) << (7 - 6)) // imm5 + | ((tinstr & 0x0038) >> 3) // Rs + | ((tinstr & 0x0007) << 12); // Rd break; case 3: // ADD/SUB - { - static const u32 subset[4] = { - 0xE0900000, // ADDS Rd,Rs,Rn - 0xE0500000, // SUBS Rd,Rs,Rn - 0xE2900000, // ADDS Rd,Rs,#imm3 - 0xE2500000 // SUBS Rd,Rs,#imm3 - }; - // It is quicker indexing into a table, than performing switch or conditionals: - *ainstr = subset[(tinstr & 0x0600) >> 9] // base opcode - |((tinstr & 0x01C0) >> 6) // Rn or imm3 - |((tinstr & 0x0038) << (16 - 3)) // Rs - |((tinstr & 0x0007) << (12 - 0)); // Rd - } - break; + { + static const u32 subset[4] = { + 0xE0900000, // ADDS Rd,Rs,Rn + 0xE0500000, // SUBS Rd,Rs,Rn + 0xE2900000, // ADDS Rd,Rs,#imm3 + 0xE2500000 // SUBS Rd,Rs,#imm3 + }; + // It is quicker indexing into a table, than performing switch or conditionals: + *ainstr = subset[(tinstr & 0x0600) >> 9] // base opcode + | ((tinstr & 0x01C0) >> 6) // Rn or imm3 + | ((tinstr & 0x0038) << (16 - 3)) // Rs + | ((tinstr & 0x0007) << (12 - 0)); // Rd + } break; case 4: // MOV case 5: // CMP case 6: // ADD case 7: // SUB - { - static const u32 subset[4] = { - 0xE3B00000, // MOVS Rd,#imm8 - 0xE3500000, // CMP Rd,#imm8 - 0xE2900000, // ADDS Rd,Rd,#imm8 - 0xE2500000, // SUBS Rd,Rd,#imm8 - }; - - *ainstr = subset[(tinstr & 0x1800) >> 11] // base opcode - |((tinstr & 0x00FF) >> 0) // imm8 - |((tinstr & 0x0700) << (16 - 8)) // Rn - |((tinstr & 0x0700) << (12 - 8)); // Rd - } - break; + { + static const u32 subset[4] = { + 0xE3B00000, // MOVS Rd,#imm8 + 0xE3500000, // CMP Rd,#imm8 + 0xE2900000, // ADDS Rd,Rd,#imm8 + 0xE2500000, // SUBS Rd,Rd,#imm8 + }; + + *ainstr = subset[(tinstr & 0x1800) >> 11] // base opcode + | ((tinstr & 0x00FF) >> 0) // imm8 + | ((tinstr & 0x0700) << (16 - 8)) // Rn + | ((tinstr & 0x0700) << (12 - 8)); // Rd + } break; case 8: // Arithmetic and high register transfers @@ -73,56 +71,51 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3 // large subset if ((tinstr & (1 << 10)) == 0) { - enum otype { - t_norm, - t_shift, - t_neg, - t_mul - }; + enum otype { t_norm, t_shift, t_neg, t_mul }; static const struct { u32 opcode; otype type; } subset[16] = { - { 0xE0100000, t_norm }, // ANDS Rd,Rd,Rs - { 0xE0300000, t_norm }, // EORS Rd,Rd,Rs - { 0xE1B00010, t_shift }, // MOVS Rd,Rd,LSL Rs - { 0xE1B00030, t_shift }, // MOVS Rd,Rd,LSR Rs - { 0xE1B00050, t_shift }, // MOVS Rd,Rd,ASR Rs - { 0xE0B00000, t_norm }, // ADCS Rd,Rd,Rs - { 0xE0D00000, t_norm }, // SBCS Rd,Rd,Rs - { 0xE1B00070, t_shift }, // MOVS Rd,Rd,ROR Rs - { 0xE1100000, t_norm }, // TST Rd,Rs - { 0xE2700000, t_neg }, // RSBS Rd,Rs,#0 - { 0xE1500000, t_norm }, // CMP Rd,Rs - { 0xE1700000, t_norm }, // CMN Rd,Rs - { 0xE1900000, t_norm }, // ORRS Rd,Rd,Rs - { 0xE0100090, t_mul }, // MULS Rd,Rd,Rs - { 0xE1D00000, t_norm }, // BICS Rd,Rd,Rs - { 0xE1F00000, t_norm } // MVNS Rd,Rs + {0xE0100000, t_norm}, // ANDS Rd,Rd,Rs + {0xE0300000, t_norm}, // EORS Rd,Rd,Rs + {0xE1B00010, t_shift}, // MOVS Rd,Rd,LSL Rs + {0xE1B00030, t_shift}, // MOVS Rd,Rd,LSR Rs + {0xE1B00050, t_shift}, // MOVS Rd,Rd,ASR Rs + {0xE0B00000, t_norm}, // ADCS Rd,Rd,Rs + {0xE0D00000, t_norm}, // SBCS Rd,Rd,Rs + {0xE1B00070, t_shift}, // MOVS Rd,Rd,ROR Rs + {0xE1100000, t_norm}, // TST Rd,Rs + {0xE2700000, t_neg}, // RSBS Rd,Rs,#0 + {0xE1500000, t_norm}, // CMP Rd,Rs + {0xE1700000, t_norm}, // CMN Rd,Rs + {0xE1900000, t_norm}, // ORRS Rd,Rd,Rs + {0xE0100090, t_mul}, // MULS Rd,Rd,Rs + {0xE1D00000, t_norm}, // BICS Rd,Rd,Rs + {0xE1F00000, t_norm} // MVNS Rd,Rs }; *ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; // base switch (subset[(tinstr & 0x03C0) >> 6].type) { case t_norm: - *ainstr |= ((tinstr & 0x0007) << 16) // Rn - |((tinstr & 0x0007) << 12) // Rd - |((tinstr & 0x0038) >> 3); // Rs + *ainstr |= ((tinstr & 0x0007) << 16) // Rn + | ((tinstr & 0x0007) << 12) // Rd + | ((tinstr & 0x0038) >> 3); // Rs break; case t_shift: - *ainstr |= ((tinstr & 0x0007) << 12) // Rd - |((tinstr & 0x0007) >> 0) // Rm - |((tinstr & 0x0038) << (8 - 3)); // Rs + *ainstr |= ((tinstr & 0x0007) << 12) // Rd + | ((tinstr & 0x0007) >> 0) // Rm + | ((tinstr & 0x0038) << (8 - 3)); // Rs break; case t_neg: - *ainstr |= ((tinstr & 0x0007) << 12) // Rd - |((tinstr & 0x0038) << (16 - 3)); // Rn + *ainstr |= ((tinstr & 0x0007) << 12) // Rd + | ((tinstr & 0x0038) << (16 - 3)); // Rn break; case t_mul: - *ainstr |= ((tinstr & 0x0007) << 16) // Rd - |((tinstr & 0x0007) << 8) // Rs - |((tinstr & 0x0038) >> 3); // Rm + *ainstr |= ((tinstr & 0x0007) << 16) // Rd + | ((tinstr & 0x0007) << 8) // Rs + | ((tinstr & 0x0038) >> 3); // Rm break; } } else { @@ -133,109 +126,106 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3 Rd += 8; switch ((tinstr & 0x03C0) >> 6) { - case 0x0: // ADD Rd,Rd,Rs - case 0x1: // ADD Rd,Rd,Hs - case 0x2: // ADD Hd,Hd,Rs - case 0x3: // ADD Hd,Hd,Hs - *ainstr = 0xE0800000 // base - | (Rd << 16) // Rn - |(Rd << 12) // Rd - |(Rs << 0); // Rm + case 0x0: // ADD Rd,Rd,Rs + case 0x1: // ADD Rd,Rd,Hs + case 0x2: // ADD Hd,Hd,Rs + case 0x3: // ADD Hd,Hd,Hs + *ainstr = 0xE0800000 // base + | (Rd << 16) // Rn + | (Rd << 12) // Rd + | (Rs << 0); // Rm break; - case 0x4: // CMP Rd,Rs - case 0x5: // CMP Rd,Hs - case 0x6: // CMP Hd,Rs - case 0x7: // CMP Hd,Hs - *ainstr = 0xE1500000 // base - | (Rd << 16) // Rn - |(Rs << 0); // Rm + case 0x4: // CMP Rd,Rs + case 0x5: // CMP Rd,Hs + case 0x6: // CMP Hd,Rs + case 0x7: // CMP Hd,Hs + *ainstr = 0xE1500000 // base + | (Rd << 16) // Rn + | (Rs << 0); // Rm break; - case 0x8: // MOV Rd,Rs - case 0x9: // MOV Rd,Hs - case 0xA: // MOV Hd,Rs - case 0xB: // MOV Hd,Hs - *ainstr = 0xE1A00000 // base - |(Rd << 12) // Rd - |(Rs << 0); // Rm + case 0x8: // MOV Rd,Rs + case 0x9: // MOV Rd,Hs + case 0xA: // MOV Hd,Rs + case 0xB: // MOV Hd,Hs + *ainstr = 0xE1A00000 // base + | (Rd << 12) // Rd + | (Rs << 0); // Rm break; - case 0xC: // BX Rs - case 0xD: // BX Hs - *ainstr = 0xE12FFF10 // base - | ((tinstr & 0x0078) >> 3); // Rd + case 0xC: // BX Rs + case 0xD: // BX Hs + *ainstr = 0xE12FFF10 // base + | ((tinstr & 0x0078) >> 3); // Rd break; - case 0xE: // BLX - case 0xF: // BLX - *ainstr = 0xE1200030 // base - | (Rs << 0); // Rm + case 0xE: // BLX + case 0xF: // BLX + *ainstr = 0xE1200030 // base + | (Rs << 0); // Rm break; } } break; - case 9: // LDR Rd,[PC,#imm8] - *ainstr = 0xE59F0000 // base - | ((tinstr & 0x0700) << (12 - 8)) // Rd - |((tinstr & 0x00FF) << (2 - 0)); // off8 + case 9: // LDR Rd,[PC,#imm8] + *ainstr = 0xE59F0000 // base + | ((tinstr & 0x0700) << (12 - 8)) // Rd + | ((tinstr & 0x00FF) << (2 - 0)); // off8 break; case 10: - case 11: - { - static const u32 subset[8] = { - 0xE7800000, // STR Rd,[Rb,Ro] - 0xE18000B0, // STRH Rd,[Rb,Ro] - 0xE7C00000, // STRB Rd,[Rb,Ro] - 0xE19000D0, // LDRSB Rd,[Rb,Ro] - 0xE7900000, // LDR Rd,[Rb,Ro] - 0xE19000B0, // LDRH Rd,[Rb,Ro] - 0xE7D00000, // LDRB Rd,[Rb,Ro] - 0xE19000F0 // LDRSH Rd,[Rb,Ro] - }; - - *ainstr = subset[(tinstr & 0xE00) >> 9] // base - |((tinstr & 0x0007) << (12 - 0)) // Rd - |((tinstr & 0x0038) << (16 - 3)) // Rb - |((tinstr & 0x01C0) >> 6); // Ro - } - break; + case 11: { + static const u32 subset[8] = { + 0xE7800000, // STR Rd,[Rb,Ro] + 0xE18000B0, // STRH Rd,[Rb,Ro] + 0xE7C00000, // STRB Rd,[Rb,Ro] + 0xE19000D0, // LDRSB Rd,[Rb,Ro] + 0xE7900000, // LDR Rd,[Rb,Ro] + 0xE19000B0, // LDRH Rd,[Rb,Ro] + 0xE7D00000, // LDRB Rd,[Rb,Ro] + 0xE19000F0 // LDRSH Rd,[Rb,Ro] + }; + + *ainstr = subset[(tinstr & 0xE00) >> 9] // base + | ((tinstr & 0x0007) << (12 - 0)) // Rd + | ((tinstr & 0x0038) << (16 - 3)) // Rb + | ((tinstr & 0x01C0) >> 6); // Ro + } break; case 12: // STR Rd,[Rb,#imm5] case 13: // LDR Rd,[Rb,#imm5] case 14: // STRB Rd,[Rb,#imm5] case 15: // LDRB Rd,[Rb,#imm5] - { - static const u32 subset[4] = { - 0xE5800000, // STR Rd,[Rb,#imm5] - 0xE5900000, // LDR Rd,[Rb,#imm5] - 0xE5C00000, // STRB Rd,[Rb,#imm5] - 0xE5D00000 // LDRB Rd,[Rb,#imm5] - }; - // The offset range defends on whether we are transferring a byte or word value: - *ainstr = subset[(tinstr & 0x1800) >> 11] // base - |((tinstr & 0x0007) << (12 - 0)) // Rd - |((tinstr & 0x0038) << (16 - 3)) // Rb - |((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); // off5 - } + { + static const u32 subset[4] = { + 0xE5800000, // STR Rd,[Rb,#imm5] + 0xE5900000, // LDR Rd,[Rb,#imm5] + 0xE5C00000, // STRB Rd,[Rb,#imm5] + 0xE5D00000 // LDRB Rd,[Rb,#imm5] + }; + // The offset range defends on whether we are transferring a byte or word value: + *ainstr = subset[(tinstr & 0x1800) >> 11] // base + | ((tinstr & 0x0007) << (12 - 0)) // Rd + | ((tinstr & 0x0038) << (16 - 3)) // Rb + | ((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); // off5 + } break; + + case 16: // STRH Rd,[Rb,#imm5] + case 17: // LDRH Rd,[Rb,#imm5] + *ainstr = ((tinstr & (1 << 11)) // base + ? 0xE1D000B0 // LDRH + : 0xE1C000B0) // STRH + | ((tinstr & 0x0007) << (12 - 0)) // Rd + | ((tinstr & 0x0038) << (16 - 3)) // Rb + | ((tinstr & 0x01C0) >> (6 - 1)) // off5, low nibble + | ((tinstr & 0x0600) >> (9 - 8)); // off5, high nibble break; - case 16: // STRH Rd,[Rb,#imm5] - case 17: // LDRH Rd,[Rb,#imm5] - *ainstr = ((tinstr & (1 << 11)) // base - ? 0xE1D000B0 // LDRH - : 0xE1C000B0) // STRH - |((tinstr & 0x0007) << (12 - 0)) // Rd - |((tinstr & 0x0038) << (16 - 3)) // Rb - |((tinstr & 0x01C0) >> (6 - 1)) // off5, low nibble - |((tinstr & 0x0600) >> (9 - 8)); // off5, high nibble - break; - - case 18: // STR Rd,[SP,#imm8] - case 19: // LDR Rd,[SP,#imm8] - *ainstr = ((tinstr & (1 << 11)) // base - ? 0xE59D0000 // LDR - : 0xE58D0000) // STR - |((tinstr & 0x0700) << (12 - 8)) // Rd - |((tinstr & 0x00FF) << 2); // off8 + case 18: // STR Rd,[SP,#imm8] + case 19: // LDR Rd,[SP,#imm8] + *ainstr = ((tinstr & (1 << 11)) // base + ? 0xE59D0000 // LDR + : 0xE58D0000) // STR + | ((tinstr & 0x0700) << (12 - 8)) // Rd + | ((tinstr & 0x00FF) << 2); // off8 break; case 20: // ADD Rd,PC,#imm8 @@ -246,14 +236,15 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3 // NOTE: The PC value used here should by word aligned. We encode shift-left-by-2 in the // rotate immediate field, so no shift of off8 is needed. - *ainstr = 0xE28F0F00 // base - | ((tinstr & 0x0700) << (12 - 8)) // Rd - |(tinstr & 0x00FF); // off8 + *ainstr = 0xE28F0F00 // base + | ((tinstr & 0x0700) << (12 - 8)) // Rd + | (tinstr & 0x00FF); // off8 } else { - // We encode shift-left-by-2 in the rotate immediate field, so no shift of off8 is needed. - *ainstr = 0xE28D0F00 // base - | ((tinstr & 0x0700) << (12 - 8)) // Rd - |(tinstr & 0x00FF); // off8 + // We encode shift-left-by-2 in the rotate immediate field, so no shift of off8 is + // needed. + *ainstr = 0xE28D0F00 // base + | ((tinstr & 0x0700) << (12 - 8)) // Rd + | (tinstr & 0x00FF); // off8 } break; @@ -261,15 +252,15 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3 case 23: if ((tinstr & 0x0F00) == 0x0000) { // NOTE: The instruction contains a shift left of 2 equivalent (implemented as ROR #30): - *ainstr = ((tinstr & (1 << 7)) // base - ? 0xE24DDF00 // SUB - : 0xE28DDF00) // ADD - |(tinstr & 0x007F); // off7 + *ainstr = ((tinstr & (1 << 7)) // base + ? 0xE24DDF00 // SUB + : 0xE28DDF00) // ADD + | (tinstr & 0x007F); // off7 } else if ((tinstr & 0x0F00) == 0x0e00) { // BKPT - *ainstr = 0xEF000000 // base - | BITS(tinstr, 0, 3) // imm4 field; - | (BITS(tinstr, 4, 7) << 8); // beginning 4 bits of imm12 + *ainstr = 0xEF000000 // base + | BITS(tinstr, 0, 3) // imm4 field; + | (BITS(tinstr, 4, 7) << 8); // beginning 4 bits of imm12 } else if ((tinstr & 0x0F00) == 0x0200) { static const u32 subset[4] = { 0xE6BF0070, // SXTH @@ -278,21 +269,21 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3 0xE6EF0070, // UXTB }; - *ainstr = subset[BITS(tinstr, 6, 7)] // base - | (BITS(tinstr, 0, 2) << 12) // Rd - | BITS(tinstr, 3, 5); // Rm + *ainstr = subset[BITS(tinstr, 6, 7)] // base + | (BITS(tinstr, 0, 2) << 12) // Rd + | BITS(tinstr, 3, 5); // Rm } else if ((tinstr & 0x0F00) == 0x600) { if (BIT(tinstr, 5) == 0) { // SETEND - *ainstr = 0xF1010000 // base - | (BIT(tinstr, 3) << 9); // endian specifier + *ainstr = 0xF1010000 // base + | (BIT(tinstr, 3) << 9); // endian specifier } else { // CPS - *ainstr = 0xF1080000 // base - | (BIT(tinstr, 0) << 6) // fiq bit - | (BIT(tinstr, 1) << 7) // irq bit - | (BIT(tinstr, 2) << 8) // abort bit - | (BIT(tinstr, 4) << 18); // enable bit + *ainstr = 0xF1080000 // base + | (BIT(tinstr, 0) << 6) // fiq bit + | (BIT(tinstr, 1) << 7) // irq bit + | (BIT(tinstr, 2) << 8) // abort bit + | (BIT(tinstr, 4) << 18); // enable bit } } else if ((tinstr & 0x0F00) == 0x0a00) { static const u32 subset[4] = { @@ -307,9 +298,9 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3 if (subset_index == 2) { valid = ThumbDecodeStatus::UNDEFINED; } else { - *ainstr = subset[subset_index] // base - | (BITS(tinstr, 0, 2) << 12) // Rd - | BITS(tinstr, 3, 5); // Rm + *ainstr = subset[subset_index] // base + | (BITS(tinstr, 0, 2) << 12) // Rd + | BITS(tinstr, 3, 5); // Rm } } else { static const u32 subset[4] = { @@ -319,14 +310,13 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3 0xE8BD8000 // LDMIA sp!,{rlist,pc} }; *ainstr = subset[((tinstr & (1 << 11)) >> 10) | ((tinstr & (1 << 8)) >> 8)] // base - |(tinstr & 0x00FF); // mask8 + | (tinstr & 0x00FF); // mask8 } break; case 24: // STMIA case 25: // LDMIA - if (tinstr & (1 << 11)) - { + if (tinstr & (1 << 11)) { unsigned int base = 0xE8900000; unsigned int rn = BITS(tinstr, 8, 10); @@ -334,15 +324,13 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3 if ((tinstr & (1 << rn)) == 0) base |= (1 << 21); - *ainstr = base // base (LDMIA) - | (rn << 16) // Rn - | (tinstr & 0x00FF); // Register list - } - else - { - *ainstr = 0xE8A00000 // base (STMIA) - | (BITS(tinstr, 8, 10) << 16) // Rn - | (tinstr & 0x00FF); // Register list + *ainstr = base // base (LDMIA) + | (rn << 16) // Rn + | (tinstr & 0x00FF); // Register list + } else { + *ainstr = 0xE8A00000 // base (STMIA) + | (BITS(tinstr, 8, 10) << 16) // Rn + | (tinstr & 0x00FF); // Register list } break; diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.h b/src/core/arm/dyncom/arm_dyncom_thumb.h index c1be3c735..231e48aa4 100644 --- a/src/core/arm/dyncom/arm_dyncom_thumb.h +++ b/src/core/arm/dyncom/arm_dyncom_thumb.h @@ -29,9 +29,9 @@ #include "common/common_types.h" enum class ThumbDecodeStatus { - UNDEFINED, // Undefined Thumb instruction - DECODED, // Instruction decoded to ARM equivalent - BRANCH, // Thumb branch (already processed) + UNDEFINED, // Undefined Thumb instruction + DECODED, // Instruction decoded to ARM equivalent + BRANCH, // Thumb branch (already processed) UNINITIALIZED, }; diff --git a/src/core/arm/dyncom/arm_dyncom_trans.cpp b/src/core/arm/dyncom/arm_dyncom_trans.cpp index 00b42c246..e056d890c 100644 --- a/src/core/arm/dyncom/arm_dyncom_trans.cpp +++ b/src/core/arm/dyncom/arm_dyncom_trans.cpp @@ -19,24 +19,23 @@ static void* AllocBuffer(size_t size) { return static_cast<void*>(&trans_cache_buf[start]); } -#define glue(x, y) x ## y +#define glue(x, y) x##y #define INTERPRETER_TRANSLATE(s) glue(InterpreterTranslate_, s) shtop_fp_t GetShifterOp(unsigned int inst); get_addr_fp_t GetAddressingOp(unsigned int inst); get_addr_fp_t GetAddressingOpLoadStoreT(unsigned int inst); -static ARM_INST_PTR INTERPRETER_TRANSLATE(adc)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(adc_inst)); - adc_inst *inst_cream = (adc_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(adc)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(adc_inst)); + adc_inst* inst_cream = (adc_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); inst_cream->Rn = BITS(inst, 16, 19); inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -47,17 +46,16 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(adc)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(add)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(add_inst)); - add_inst *inst_cream = (add_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(add)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(add_inst)); + add_inst* inst_cream = (add_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); inst_cream->Rn = BITS(inst, 16, 19); inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -68,17 +66,16 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(add)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(and)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(and_inst)); - and_inst *inst_cream = (and_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(and)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(and_inst)); + and_inst* inst_cream = (and_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); inst_cream->Rn = BITS(inst, 16, 19); inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -89,37 +86,35 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(and)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(bbl)(unsigned int inst, int index) -{ - #define POSBRANCH ((inst & 0x7fffff) << 2) - #define NEGBRANCH ((0xff000000 |(inst & 0xffffff)) << 2) +static ARM_INST_PTR INTERPRETER_TRANSLATE(bbl)(unsigned int inst, int index) { +#define POSBRANCH ((inst & 0x7fffff) << 2) +#define NEGBRANCH ((0xff000000 | (inst & 0xffffff)) << 2) - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bbl_inst)); - bbl_inst *inst_cream = (bbl_inst *)inst_base->component; + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bbl_inst)); + bbl_inst* inst_cream = (bbl_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::DIRECT_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::DIRECT_BRANCH; if (BIT(inst, 24)) inst_base->br = TransExtData::CALL; - inst_cream->L = BIT(inst, 24); + inst_cream->L = BIT(inst, 24); inst_cream->signed_immed_24 = BIT(inst, 23) ? NEGBRANCH : POSBRANCH; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(bic)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bic_inst)); - bic_inst *inst_cream = (bic_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(bic)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bic_inst)); + bic_inst* inst_cream = (bic_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); inst_cream->Rn = BITS(inst, 16, 19); inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -130,28 +125,26 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(bic)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(bkpt)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(bkpt)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bkpt_inst)); bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->imm = (BITS(inst, 8, 19) << 4) | BITS(inst, 0, 3); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(blx)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(blx_inst)); - blx_inst *inst_cream = (blx_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(blx)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(blx_inst)); + blx_inst* inst_cream = (blx_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::INDIRECT_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::INDIRECT_BRANCH; inst_cream->inst = inst; if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) { @@ -162,36 +155,34 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(blx)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(bx)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bx_inst)); - bx_inst *inst_cream = (bx_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(bx)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bx_inst)); + bx_inst* inst_cream = (bx_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::INDIRECT_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::INDIRECT_BRANCH; - inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rm = BITS(inst, 0, 3); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(bxj)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(bxj)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(bx)(inst, index); } static ARM_INST_PTR INTERPRETER_TRANSLATE(cdp)(unsigned int inst, int index) { - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cdp_inst)); - cdp_inst *inst_cream = (cdp_inst *)inst_base->component; + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(cdp_inst)); + cdp_inst* inst_cream = (cdp_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->CRm = BITS(inst, 0, 3); - inst_cream->CRd = BITS(inst, 12, 15); - inst_cream->CRn = BITS(inst, 16, 19); - inst_cream->cp_num = BITS(inst, 8, 11); + inst_cream->CRm = BITS(inst, 0, 3); + inst_cream->CRd = BITS(inst, 12, 15); + inst_cream->CRn = BITS(inst, 16, 19); + inst_cream->cp_num = BITS(inst, 8, 11); inst_cream->opcode_2 = BITS(inst, 5, 7); inst_cream->opcode_1 = BITS(inst, 20, 23); inst_cream->inst = inst; @@ -199,91 +190,85 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(cdp)(unsigned int inst, int index) { LOG_TRACE(Core_ARM11, "inst %x index %x", inst, index); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(clrex)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(clrex_inst)); +static ARM_INST_PTR INTERPRETER_TRANSLATE(clrex)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(clrex_inst)); inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(clz)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(clz_inst)); - clz_inst *inst_cream = (clz_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(clz)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(clz_inst)); + clz_inst* inst_cream = (clz_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rm = BITS(inst, 0, 3); inst_cream->Rd = BITS(inst, 12, 15); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(cmn)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cmn_inst)); - cmn_inst *inst_cream = (cmn_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(cmn)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(cmn_inst)); + cmn_inst* inst_cream = (cmn_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); + inst_cream->I = BIT(inst, 25); inst_cream->Rn = BITS(inst, 16, 19); inst_cream->shifter_operand = BITS(inst, 0, 11); inst_cream->shtop_func = GetShifterOp(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(cmp)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cmp_inst)); - cmp_inst *inst_cream = (cmp_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(cmp)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(cmp_inst)); + cmp_inst* inst_cream = (cmp_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); + inst_cream->I = BIT(inst, 25); inst_cream->Rn = BITS(inst, 16, 19); inst_cream->shifter_operand = BITS(inst, 0, 11); inst_cream->shtop_func = GetShifterOp(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(cps)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cps_inst)); - cps_inst *inst_cream = (cps_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(cps)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(cps_inst)); + cps_inst* inst_cream = (cps_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->imod0 = BIT(inst, 18); inst_cream->imod1 = BIT(inst, 19); - inst_cream->mmod = BIT(inst, 17); - inst_cream->A = BIT(inst, 8); - inst_cream->I = BIT(inst, 7); - inst_cream->F = BIT(inst, 6); - inst_cream->mode = BITS(inst, 0, 4); + inst_cream->mmod = BIT(inst, 17); + inst_cream->A = BIT(inst, 8); + inst_cream->I = BIT(inst, 7); + inst_cream->F = BIT(inst, 6); + inst_cream->mode = BITS(inst, 0, 4); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(cpy)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mov_inst)); - mov_inst *inst_cream = (mov_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(cpy)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mov_inst)); + mov_inst* inst_cream = (mov_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); inst_cream->shtop_func = GetShifterOp(inst); @@ -293,17 +278,16 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(cpy)(unsigned int inst, int index) } return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(eor)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(eor_inst)); - eor_inst *inst_cream = (eor_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(eor)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(eor_inst)); + eor_inst* inst_cream = (eor_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); inst_cream->Rn = BITS(inst, 16, 19); inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -314,23 +298,21 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(eor)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ldc)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldc_inst)); +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldc)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldc_inst)); inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ldm)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldm)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOp(inst); @@ -340,29 +322,27 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldm)(unsigned int inst, int index) } return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(sxth)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtb_inst)); - sxtb_inst *inst_cream = (sxtb_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxth)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sxtb_inst)); + sxtb_inst* inst_cream = (sxtb_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rd = BITS(inst, 12, 15); - inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); inst_cream->rotate = BITS(inst, 10, 11); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ldr)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldr)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOp(inst); @@ -373,14 +353,13 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldr)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrcond)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrcond)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOp(inst); @@ -391,155 +370,143 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrcond)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uxth)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxth_inst)); - uxth_inst *inst_cream = (uxth_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxth)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(uxth_inst)); + uxth_inst* inst_cream = (uxth_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->rotate = BITS(inst, 10, 11); - inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rm = BITS(inst, 0, 3); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtah)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxtah_inst)); - uxtah_inst *inst_cream = (uxtah_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtah)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(uxtah_inst)); + uxtah_inst* inst_cream = (uxtah_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->rotate = BITS(inst, 10, 11); - inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rm = BITS(inst, 0, 3); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrb)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrb)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOp(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index) { arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOpLoadStoreT(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrd)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrd)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOp(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrex)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); - generic_arm_inst *inst_cream = (generic_arm_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrex)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = (BITS(inst, 12, 15) == 15) ? TransExtData::INDIRECT_BRANCH : TransExtData::NON_BRANCH; // Branch if dest is R15 + inst_base->idx = index; + inst_base->br = (BITS(inst, 12, 15) == 15) ? TransExtData::INDIRECT_BRANCH + : TransExtData::NON_BRANCH; // Branch if dest is R15 inst_cream->Rn = BITS(inst, 16, 19); inst_cream->Rd = BITS(inst, 12, 15); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexb)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexb)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(ldrex)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexh)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexh)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(ldrex)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexd)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexd)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(ldrex)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrh)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrh)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOp(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOp(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOp(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index) { arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOpLoadStoreT(inst); @@ -549,70 +516,66 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index) } return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(mcr)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mcr_inst)); - mcr_inst *inst_cream = (mcr_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(mcr)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mcr_inst)); + mcr_inst* inst_cream = (mcr_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->crn = BITS(inst, 16, 19); - inst_cream->crm = BITS(inst, 0, 3); + inst_cream->crn = BITS(inst, 16, 19); + inst_cream->crm = BITS(inst, 0, 3); inst_cream->opcode_1 = BITS(inst, 21, 23); - inst_cream->opcode_2 = BITS(inst, 5, 7); - inst_cream->Rd = BITS(inst, 12, 15); - inst_cream->cp_num = BITS(inst, 8, 11); - inst_cream->inst = inst; + inst_cream->opcode_2 = BITS(inst, 5, 7); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->cp_num = BITS(inst, 8, 11); + inst_cream->inst = inst; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(mcrr)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(mcrr)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mcrr_inst)); mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->crm = BITS(inst, 0, 3); + inst_cream->crm = BITS(inst, 0, 3); inst_cream->opcode_1 = BITS(inst, 4, 7); - inst_cream->cp_num = BITS(inst, 8, 11); - inst_cream->rt = BITS(inst, 12, 15); - inst_cream->rt2 = BITS(inst, 16, 19); + inst_cream->cp_num = BITS(inst, 8, 11); + inst_cream->rt = BITS(inst, 12, 15); + inst_cream->rt2 = BITS(inst, 16, 19); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(mla)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mla_inst)); - mla_inst *inst_cream = (mla_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(mla)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mla_inst)); + mla_inst* inst_cream = (mla_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->S = BIT(inst, 20); + inst_cream->S = BIT(inst, 20); inst_cream->Rn = BITS(inst, 12, 15); inst_cream->Rd = BITS(inst, 16, 19); - inst_cream->Rs = BITS(inst, 8, 11); - inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->Rm = BITS(inst, 0, 3); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(mov)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mov_inst)); - mov_inst *inst_cream = (mov_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(mov)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mov_inst)); + mov_inst* inst_cream = (mov_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); inst_cream->shtop_func = GetShifterOp(inst); @@ -622,85 +585,79 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(mov)(unsigned int inst, int index) } return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(mrc)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mrc_inst)); - mrc_inst *inst_cream = (mrc_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(mrc)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mrc_inst)); + mrc_inst* inst_cream = (mrc_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->crn = BITS(inst, 16, 19); - inst_cream->crm = BITS(inst, 0, 3); + inst_cream->crn = BITS(inst, 16, 19); + inst_cream->crm = BITS(inst, 0, 3); inst_cream->opcode_1 = BITS(inst, 21, 23); - inst_cream->opcode_2 = BITS(inst, 5, 7); - inst_cream->Rd = BITS(inst, 12, 15); - inst_cream->cp_num = BITS(inst, 8, 11); - inst_cream->inst = inst; + inst_cream->opcode_2 = BITS(inst, 5, 7); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->cp_num = BITS(inst, 8, 11); + inst_cream->inst = inst; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(mrrc)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(mrrc)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(mcrr)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(mrs)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mrs_inst)); - mrs_inst *inst_cream = (mrs_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(mrs)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mrs_inst)); + mrs_inst* inst_cream = (mrs_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->Rd = BITS(inst, 12, 15); - inst_cream->R = BIT(inst, 22); + inst_cream->R = BIT(inst, 22); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(msr)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(msr_inst)); - msr_inst *inst_cream = (msr_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(msr)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(msr_inst)); + msr_inst* inst_cream = (msr_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->field_mask = BITS(inst, 16, 19); - inst_cream->R = BIT(inst, 22); - inst_cream->inst = inst; + inst_cream->R = BIT(inst, 22); + inst_cream->inst = inst; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(mul)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mul_inst)); - mul_inst *inst_cream = (mul_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(mul)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mul_inst)); + mul_inst* inst_cream = (mul_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->S = BIT(inst, 20); + inst_cream->S = BIT(inst, 20); inst_cream->Rm = BITS(inst, 0, 3); inst_cream->Rs = BITS(inst, 8, 11); inst_cream->Rd = BITS(inst, 16, 19); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(mvn)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mvn_inst)); - mvn_inst *inst_cream = (mvn_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(mvn)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mvn_inst)); + mvn_inst* inst_cream = (mvn_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); inst_cream->shtop_func = GetShifterOp(inst); @@ -709,19 +666,17 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(mvn)(unsigned int inst, int index) inst_base->br = TransExtData::INDIRECT_BRANCH; } return inst_base; - } -static ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(orr_inst)); - orr_inst *inst_cream = (orr_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(orr_inst)); + orr_inst* inst_cream = (orr_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); inst_cream->Rd = BITS(inst, 12, 15); inst_cream->Rn = BITS(inst, 16, 19); inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -734,150 +689,132 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(unsigned int inst, int index) } // NOP introduced in ARMv6K. -static ARM_INST_PTR INTERPRETER_TRANSLATE(nop)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(nop)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst)); inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pkh_inst)); - pkh_inst *inst_cream = (pkh_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(pkh_inst)); + pkh_inst* inst_cream = (pkh_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rd = BITS(inst, 12, 15); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rm = BITS(inst, 0, 3); inst_cream->imm = BITS(inst, 7, 11); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhtb)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhtb)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(pkhbt)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(pld)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pld_inst)); +static ARM_INST_PTR INTERPRETER_TRANSLATE(pld)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(pld_inst)); inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->op1 = BITS(inst, 21, 22); - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd8)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd8)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->op1 = BITS(inst, 20, 21); inst_cream->op2 = BITS(inst, 5, 7); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(qaddsubx)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(qaddsubx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub8)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub8)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(qsubaddx)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(qsubaddx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(rev)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(rev)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(rev_inst)); rev_inst* const inst_cream = (rev_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->op1 = BITS(inst, 20, 22); inst_cream->op2 = BITS(inst, 5, 7); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(rev16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(rev16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(rev)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(revsh)(unsigned int inst, int index) -{ - return INTERPRETER_TRANSLATE(rev)(inst, index); +static ARM_INST_PTR INTERPRETER_TRANSLATE(revsh)(unsigned int inst, int index) { + return INTERPRETER_TRANSLATE(rev)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = AL; - inst_base->idx = index; - inst_base->br = TransExtData::INDIRECT_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::INDIRECT_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOp(inst); @@ -885,17 +822,16 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rsb_inst)); - rsb_inst *inst_cream = (rsb_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(rsb_inst)); + rsb_inst* inst_cream = (rsb_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); inst_cream->Rn = BITS(inst, 16, 19); inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -906,17 +842,16 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(rsc)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rsc_inst)); - rsc_inst *inst_cream = (rsc_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(rsc)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(rsc_inst)); + rsc_inst* inst_cream = (rsc_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); inst_cream->Rn = BITS(inst, 16, 19); inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -927,55 +862,48 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(rsc)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(sadd8)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(sadd8)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->op1 = BITS(inst, 20, 21); inst_cream->op2 = BITS(inst, 5, 7); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(sadd16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(sadd16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(sadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(saddsubx)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(saddsubx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(sadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ssub8)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(ssub8)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(sadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ssub16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(ssub16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(sadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ssubaddx)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(ssubaddx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(sadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(sbc)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sbc_inst)); - sbc_inst *inst_cream = (sbc_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(sbc)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sbc_inst)); + sbc_inst* inst_cream = (sbc_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); inst_cream->Rn = BITS(inst, 16, 19); inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -986,98 +914,88 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(sbc)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(sel)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(sel)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->op1 = BITS(inst, 20, 22); inst_cream->op2 = BITS(inst, 5, 7); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(setend_inst)); setend_inst* const inst_cream = (setend_inst*)inst_base->component; inst_base->cond = AL; - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->set_bigend = BIT(inst, 9); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(sev)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(sev)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst)); inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->op1 = BITS(inst, 20, 21); inst_cream->op2 = BITS(inst, 5, 7); - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(shadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(shaddsubx)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(shaddsubx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(shadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(shsub8)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(shsub8)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(shadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(shsub16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(shsub16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(shadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(shsubaddx)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(shsubaddx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(shadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smla)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smla_inst)); - smla_inst *inst_cream = (smla_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(smla)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smla_inst)); + smla_inst* inst_cream = (smla_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->x = BIT(inst, 5); - inst_cream->y = BIT(inst, 6); + inst_cream->x = BIT(inst, 5); + inst_cream->y = BIT(inst, 6); inst_cream->Rm = BITS(inst, 0, 3); inst_cream->Rs = BITS(inst, 8, 11); inst_cream->Rd = BITS(inst, 16, 19); @@ -1086,192 +1004,176 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(smla)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smlad)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlad)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst)); smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->m = BIT(inst, 5); - inst_cream->Rn = BITS(inst, 0, 3); - inst_cream->Rm = BITS(inst, 8, 11); - inst_cream->Rd = BITS(inst, 16, 19); - inst_cream->Ra = BITS(inst, 12, 15); + inst_cream->m = BIT(inst, 5); + inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->Rm = BITS(inst, 8, 11); + inst_cream->Rd = BITS(inst, 16, 19); + inst_cream->Ra = BITS(inst, 12, 15); inst_cream->op1 = BITS(inst, 20, 22); inst_cream->op2 = BITS(inst, 5, 7); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smuad)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(smuad)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(smlad)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smusd)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(smusd)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(smlad)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smlsd)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlsd)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(smlad)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umlal_inst)); - umlal_inst *inst_cream = (umlal_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(umlal_inst)); + umlal_inst* inst_cream = (umlal_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->S = BIT(inst, 20); - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->S = BIT(inst, 20); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); inst_cream->RdHi = BITS(inst, 16, 19); inst_cream->RdLo = BITS(inst, 12, 15); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlalxy_inst)); smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->x = BIT(inst, 5); - inst_cream->y = BIT(inst, 6); + inst_cream->x = BIT(inst, 5); + inst_cream->y = BIT(inst, 6); inst_cream->RdLo = BITS(inst, 12, 15); inst_cream->RdHi = BITS(inst, 16, 19); - inst_cream->Rn = BITS(inst, 0, 4); - inst_cream->Rm = BITS(inst, 8, 11); + inst_cream->Rn = BITS(inst, 0, 4); + inst_cream->Rm = BITS(inst, 8, 11); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst)); smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->Ra = BITS(inst, 12, 15); inst_cream->Rm = BITS(inst, 8, 11); inst_cream->Rn = BITS(inst, 0, 3); inst_cream->Rd = BITS(inst, 16, 19); - inst_cream->m = BIT(inst, 6); + inst_cream->m = BIT(inst, 6); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smlald)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlald)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlald_inst)); smlald_inst* const inst_cream = (smlald_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rm = BITS(inst, 8, 11); - inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->Rm = BITS(inst, 8, 11); + inst_cream->Rn = BITS(inst, 0, 3); inst_cream->RdLo = BITS(inst, 12, 15); inst_cream->RdHi = BITS(inst, 16, 19); inst_cream->swap = BIT(inst, 5); - inst_cream->op1 = BITS(inst, 20, 22); - inst_cream->op2 = BITS(inst, 5, 7); + inst_cream->op1 = BITS(inst, 20, 22); + inst_cream->op2 = BITS(inst, 5, 7); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smlsld)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlsld)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(smlald)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smmla)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(smmla)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst)); smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->m = BIT(inst, 5); - inst_cream->Ra = BITS(inst, 12, 15); - inst_cream->Rm = BITS(inst, 8, 11); - inst_cream->Rn = BITS(inst, 0, 3); - inst_cream->Rd = BITS(inst, 16, 19); + inst_cream->m = BIT(inst, 5); + inst_cream->Ra = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 8, 11); + inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->Rd = BITS(inst, 16, 19); inst_cream->op1 = BITS(inst, 20, 22); inst_cream->op2 = BITS(inst, 5, 7); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smmls)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(smmls)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(smmla)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smmul)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(smmul)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(smmla)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smul)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smul_inst)); - smul_inst *inst_cream = (smul_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(smul)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smul_inst)); + smul_inst* inst_cream = (smul_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->Rd = BITS(inst, 16, 19); - inst_cream->Rs = BITS(inst, 8, 11); - inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->x = BIT(inst, 5); - inst_cream->y = BIT(inst, 6); + inst_cream->x = BIT(inst, 5); + inst_cream->y = BIT(inst, 6); return inst_base; - } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smull)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umull_inst)); - umull_inst *inst_cream = (umull_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(smull)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(umull_inst)); + umull_inst* inst_cream = (umull_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->S = BIT(inst, 20); - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->S = BIT(inst, 20); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); inst_cream->RdHi = BITS(inst, 16, 19); inst_cream->RdLo = BITS(inst, 12, 15); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst)); - smlad_inst *inst_cream = (smlad_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst)); + smlad_inst* inst_cream = (smlad_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->m = BIT(inst, 6); + inst_cream->m = BIT(inst, 6); inst_cream->Rm = BITS(inst, 8, 11); inst_cream->Rn = BITS(inst, 0, 3); inst_cream->Rd = BITS(inst, 16, 19); @@ -1279,29 +1181,27 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = AL; - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->inst = inst; + inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOp(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst)); ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->Rn = BITS(inst, 0, 3); inst_cream->Rd = BITS(inst, 12, 15); @@ -1311,211 +1211,195 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat16)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst)); ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rn = BITS(inst, 0, 3); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->sat_imm = BITS(inst, 16, 19); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(stc)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(stc_inst)); +static ARM_INST_PTR INTERPRETER_TRANSLATE(stc)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(stc_inst)); inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(stm)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(stm)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOp(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtb_inst)); - sxtb_inst *inst_cream = (sxtb_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sxtb_inst)); + sxtb_inst* inst_cream = (sxtb_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rd = BITS(inst, 12, 15); - inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); inst_cream->rotate = BITS(inst, 10, 11); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(str)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(str)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOp(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxth_inst)); - uxth_inst *inst_cream = (uxth_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(uxth_inst)); + uxth_inst* inst_cream = (uxth_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->rotate = BITS(inst, 10, 11); - inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rm = BITS(inst, 0, 3); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxtab_inst)); - uxtab_inst *inst_cream = (uxtab_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(uxtab_inst)); + uxtab_inst* inst_cream = (uxtab_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->rotate = BITS(inst, 10, 11); - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(strb)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(strb)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOp(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index) { arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOpLoadStoreT(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOp(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); - generic_arm_inst *inst_cream = (generic_arm_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); - inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(strexb)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(strexb)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(strex)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(strexh)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(strexh)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(strex)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(strexd)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(strexd)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(strex)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(strh)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(strh)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOp(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index) { arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = GetAddressingOpLoadStoreT(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sub_inst)); - sub_inst *inst_cream = (sub_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sub_inst)); + sub_inst* inst_cream = (sub_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); inst_cream->Rn = BITS(inst, 16, 19); inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -1526,71 +1410,68 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(swi)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(swi_inst)); - swi_inst *inst_cream = (swi_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(swi)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(swi_inst)); + swi_inst* inst_cream = (swi_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->num = BITS(inst, 0, 23); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(swp)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(swp_inst)); - swp_inst *inst_cream = (swp_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(swp)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(swp_inst)); + swp_inst* inst_cream = (swp_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); - inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index){ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(swp_inst)); - swp_inst *inst_cream = (swp_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(swp_inst)); + swp_inst* inst_cream = (swp_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); - inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab)(unsigned int inst, int index){ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtab_inst)); - sxtab_inst *inst_cream = (sxtab_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sxtab_inst)); + sxtab_inst* inst_cream = (sxtab_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->rotate = BITS(inst, 10, 11); - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab16)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sxtab_inst)); sxtab_inst* const inst_cream = (sxtab_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->Rm = BITS(inst, 0, 3); inst_cream->Rn = BITS(inst, 16, 19); @@ -1599,54 +1480,51 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab16)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(sxtab16)(inst, index); } static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtah)(unsigned int inst, int index) { - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtah_inst)); - sxtah_inst *inst_cream = (sxtah_inst *)inst_base->component; + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sxtah_inst)); + sxtah_inst* inst_cream = (sxtah_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->rotate = BITS(inst, 10, 11); - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(teq)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(teq_inst)); - teq_inst *inst_cream = (teq_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(teq)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(teq_inst)); + teq_inst* inst_cream = (teq_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->I = BIT(inst, 25); + inst_cream->Rn = BITS(inst, 16, 19); inst_cream->shifter_operand = BITS(inst, 0, 11); - inst_cream->shtop_func = GetShifterOp(inst); + inst_cream->shtop_func = GetShifterOp(inst); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(tst)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(tst_inst)); - tst_inst *inst_cream = (tst_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(tst)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(tst_inst)); + tst_inst* inst_cream = (tst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); inst_cream->Rn = BITS(inst, 16, 19); inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -1655,309 +1533,274 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(tst)(unsigned int inst, int index) return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uadd8)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uadd8)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->op1 = BITS(inst, 20, 21); inst_cream->op2 = BITS(inst, 5, 7); - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uadd16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uadd16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uaddsubx)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uaddsubx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(usub8)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(usub8)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(usub16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(usub16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(usubaddx)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(usubaddx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd8)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd8)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->op1 = BITS(inst, 20, 21); inst_cream->op2 = BITS(inst, 5, 7); - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uhadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uhaddsubx)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhaddsubx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uhadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub8)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub8)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uhadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uhadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsubaddx)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsubaddx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uhadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(umaal)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(umaal)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(umaal_inst)); umaal_inst* const inst_cream = (umaal_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rm = BITS(inst, 8, 11); - inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->Rm = BITS(inst, 8, 11); + inst_cream->Rn = BITS(inst, 0, 3); inst_cream->RdLo = BITS(inst, 12, 15); inst_cream->RdHi = BITS(inst, 16, 19); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(umlal)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umlal_inst)); - umlal_inst *inst_cream = (umlal_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(umlal)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(umlal_inst)); + umlal_inst* inst_cream = (umlal_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->S = BIT(inst, 20); - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->S = BIT(inst, 20); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); inst_cream->RdHi = BITS(inst, 16, 19); inst_cream->RdLo = BITS(inst, 12, 15); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(umull)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umull_inst)); - umull_inst *inst_cream = (umull_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(umull)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(umull_inst)); + umull_inst* inst_cream = (umull_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->S = BIT(inst, 20); - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->S = BIT(inst, 20); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); inst_cream->RdHi = BITS(inst, 16, 19); inst_cream->RdLo = BITS(inst, 12, 15); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(b_2_thumb)(unsigned int tinst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(b_2_thumb)); - b_2_thumb *inst_cream = (b_2_thumb *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(b_2_thumb)(unsigned int tinst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(b_2_thumb)); + b_2_thumb* inst_cream = (b_2_thumb*)inst_base->component; inst_cream->imm = ((tinst & 0x3FF) << 1) | ((tinst & (1 << 10)) ? 0xFFFFF800 : 0); inst_base->idx = index; - inst_base->br = TransExtData::DIRECT_BRANCH; + inst_base->br = TransExtData::DIRECT_BRANCH; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(b_cond_thumb)(unsigned int tinst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(b_cond_thumb)); - b_cond_thumb *inst_cream = (b_cond_thumb *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(b_cond_thumb)(unsigned int tinst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(b_cond_thumb)); + b_cond_thumb* inst_cream = (b_cond_thumb*)inst_base->component; - inst_cream->imm = (((tinst & 0x7F) << 1) | ((tinst & (1 << 7)) ? 0xFFFFFF00 : 0)); + inst_cream->imm = (((tinst & 0x7F) << 1) | ((tinst & (1 << 7)) ? 0xFFFFFF00 : 0)); inst_cream->cond = ((tinst >> 8) & 0xf); - inst_base->idx = index; - inst_base->br = TransExtData::DIRECT_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::DIRECT_BRANCH; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(bl_1_thumb)(unsigned int tinst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bl_1_thumb)); - bl_1_thumb *inst_cream = (bl_1_thumb *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(bl_1_thumb)(unsigned int tinst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bl_1_thumb)); + bl_1_thumb* inst_cream = (bl_1_thumb*)inst_base->component; inst_cream->imm = (((tinst & 0x07FF) << 12) | ((tinst & (1 << 10)) ? 0xFF800000 : 0)); inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->br = TransExtData::NON_BRANCH; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(bl_2_thumb)(unsigned int tinst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bl_2_thumb)); - bl_2_thumb *inst_cream = (bl_2_thumb *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(bl_2_thumb)(unsigned int tinst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bl_2_thumb)); + bl_2_thumb* inst_cream = (bl_2_thumb*)inst_base->component; inst_cream->imm = (tinst & 0x07FF) << 1; inst_base->idx = index; - inst_base->br = TransExtData::DIRECT_BRANCH; + inst_base->br = TransExtData::DIRECT_BRANCH; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(blx_1_thumb)(unsigned int tinst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(blx_1_thumb)); - blx_1_thumb *inst_cream = (blx_1_thumb *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(blx_1_thumb)(unsigned int tinst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(blx_1_thumb)); + blx_1_thumb* inst_cream = (blx_1_thumb*)inst_base->component; - inst_cream->imm = (tinst & 0x07FF) << 1; + inst_cream->imm = (tinst & 0x07FF) << 1; inst_cream->instr = tinst; - inst_base->idx = index; - inst_base->br = TransExtData::DIRECT_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::DIRECT_BRANCH; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd8)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd8)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->op1 = BITS(inst, 20, 21); inst_cream->op2 = BITS(inst, 5, 7); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uqadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uqaddsubx)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqaddsubx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uqadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub8)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub8)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uqadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uqadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsubaddx)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsubaddx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uqadd8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(usada8)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(usada8)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->op1 = BITS(inst, 20, 24); inst_cream->op2 = BITS(inst, 5, 7); - inst_cream->Rd = BITS(inst, 16, 19); - inst_cream->Rm = BITS(inst, 8, 11); - inst_cream->Rn = BITS(inst, 0, 3); - inst_cream->Ra = BITS(inst, 12, 15); + inst_cream->Rd = BITS(inst, 16, 19); + inst_cream->Rm = BITS(inst, 8, 11); + inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->Ra = BITS(inst, 12, 15); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(usad8)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(usad8)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(usada8)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(usat)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(usat)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(ssat)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(usat16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(usat16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(ssat16)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab16)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(uxtab_inst)); uxtab_inst* const inst_cream = (uxtab_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->rotate = BITS(inst, 10, 11); return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb16)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uxtab16)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(wfe)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(wfe)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst)); inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(wfi)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(wfi)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst)); inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(yield)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(yield)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst)); inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; return inst_base; } @@ -1968,211 +1811,78 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(yield)(unsigned int inst, int index) #undef VFP_INTERPRETER_TRANS const transop_fp_t arm_instruction_trans[] = { - INTERPRETER_TRANSLATE(vmla), - INTERPRETER_TRANSLATE(vmls), - INTERPRETER_TRANSLATE(vnmla), - INTERPRETER_TRANSLATE(vnmls), - INTERPRETER_TRANSLATE(vnmul), - INTERPRETER_TRANSLATE(vmul), - INTERPRETER_TRANSLATE(vadd), - INTERPRETER_TRANSLATE(vsub), - INTERPRETER_TRANSLATE(vdiv), - INTERPRETER_TRANSLATE(vmovi), - INTERPRETER_TRANSLATE(vmovr), - INTERPRETER_TRANSLATE(vabs), - INTERPRETER_TRANSLATE(vneg), - INTERPRETER_TRANSLATE(vsqrt), - INTERPRETER_TRANSLATE(vcmp), - INTERPRETER_TRANSLATE(vcmp2), - INTERPRETER_TRANSLATE(vcvtbds), - INTERPRETER_TRANSLATE(vcvtbff), - INTERPRETER_TRANSLATE(vcvtbfi), - INTERPRETER_TRANSLATE(vmovbrs), - INTERPRETER_TRANSLATE(vmsr), - INTERPRETER_TRANSLATE(vmovbrc), - INTERPRETER_TRANSLATE(vmrs), - INTERPRETER_TRANSLATE(vmovbcr), - INTERPRETER_TRANSLATE(vmovbrrss), - INTERPRETER_TRANSLATE(vmovbrrd), - INTERPRETER_TRANSLATE(vstr), - INTERPRETER_TRANSLATE(vpush), - INTERPRETER_TRANSLATE(vstm), - INTERPRETER_TRANSLATE(vpop), - INTERPRETER_TRANSLATE(vldr), - INTERPRETER_TRANSLATE(vldm), - - INTERPRETER_TRANSLATE(srs), - INTERPRETER_TRANSLATE(rfe), - INTERPRETER_TRANSLATE(bkpt), - INTERPRETER_TRANSLATE(blx), - INTERPRETER_TRANSLATE(cps), - INTERPRETER_TRANSLATE(pld), - INTERPRETER_TRANSLATE(setend), - INTERPRETER_TRANSLATE(clrex), - INTERPRETER_TRANSLATE(rev16), - INTERPRETER_TRANSLATE(usad8), - INTERPRETER_TRANSLATE(sxtb), - INTERPRETER_TRANSLATE(uxtb), - INTERPRETER_TRANSLATE(sxth), - INTERPRETER_TRANSLATE(sxtb16), - INTERPRETER_TRANSLATE(uxth), - INTERPRETER_TRANSLATE(uxtb16), - INTERPRETER_TRANSLATE(cpy), - INTERPRETER_TRANSLATE(uxtab), - INTERPRETER_TRANSLATE(ssub8), - INTERPRETER_TRANSLATE(shsub8), - INTERPRETER_TRANSLATE(ssubaddx), - INTERPRETER_TRANSLATE(strex), - INTERPRETER_TRANSLATE(strexb), - INTERPRETER_TRANSLATE(swp), - INTERPRETER_TRANSLATE(swpb), - INTERPRETER_TRANSLATE(ssub16), - INTERPRETER_TRANSLATE(ssat16), - INTERPRETER_TRANSLATE(shsubaddx), - INTERPRETER_TRANSLATE(qsubaddx), - INTERPRETER_TRANSLATE(shaddsubx), - INTERPRETER_TRANSLATE(shadd8), - INTERPRETER_TRANSLATE(shadd16), - INTERPRETER_TRANSLATE(sel), - INTERPRETER_TRANSLATE(saddsubx), - INTERPRETER_TRANSLATE(sadd8), - INTERPRETER_TRANSLATE(sadd16), - INTERPRETER_TRANSLATE(shsub16), - INTERPRETER_TRANSLATE(umaal), - INTERPRETER_TRANSLATE(uxtab16), - INTERPRETER_TRANSLATE(usubaddx), - INTERPRETER_TRANSLATE(usub8), - INTERPRETER_TRANSLATE(usub16), - INTERPRETER_TRANSLATE(usat16), - INTERPRETER_TRANSLATE(usada8), - INTERPRETER_TRANSLATE(uqsubaddx), - INTERPRETER_TRANSLATE(uqsub8), - INTERPRETER_TRANSLATE(uqsub16), - INTERPRETER_TRANSLATE(uqaddsubx), - INTERPRETER_TRANSLATE(uqadd8), - INTERPRETER_TRANSLATE(uqadd16), - INTERPRETER_TRANSLATE(sxtab), - INTERPRETER_TRANSLATE(uhsubaddx), - INTERPRETER_TRANSLATE(uhsub8), - INTERPRETER_TRANSLATE(uhsub16), - INTERPRETER_TRANSLATE(uhaddsubx), - INTERPRETER_TRANSLATE(uhadd8), - INTERPRETER_TRANSLATE(uhadd16), - INTERPRETER_TRANSLATE(uaddsubx), - INTERPRETER_TRANSLATE(uadd8), - INTERPRETER_TRANSLATE(uadd16), - INTERPRETER_TRANSLATE(sxtah), - INTERPRETER_TRANSLATE(sxtab16), - INTERPRETER_TRANSLATE(qadd8), - INTERPRETER_TRANSLATE(bxj), - INTERPRETER_TRANSLATE(clz), - INTERPRETER_TRANSLATE(uxtah), - INTERPRETER_TRANSLATE(bx), - INTERPRETER_TRANSLATE(rev), - INTERPRETER_TRANSLATE(blx), - INTERPRETER_TRANSLATE(revsh), - INTERPRETER_TRANSLATE(qadd), - INTERPRETER_TRANSLATE(qadd16), - INTERPRETER_TRANSLATE(qaddsubx), - INTERPRETER_TRANSLATE(ldrex), - INTERPRETER_TRANSLATE(qdadd), - INTERPRETER_TRANSLATE(qdsub), - INTERPRETER_TRANSLATE(qsub), - INTERPRETER_TRANSLATE(ldrexb), - INTERPRETER_TRANSLATE(qsub8), - INTERPRETER_TRANSLATE(qsub16), - INTERPRETER_TRANSLATE(smuad), - INTERPRETER_TRANSLATE(smmul), - INTERPRETER_TRANSLATE(smusd), - INTERPRETER_TRANSLATE(smlsd), - INTERPRETER_TRANSLATE(smlsld), - INTERPRETER_TRANSLATE(smmla), - INTERPRETER_TRANSLATE(smmls), - INTERPRETER_TRANSLATE(smlald), - INTERPRETER_TRANSLATE(smlad), - INTERPRETER_TRANSLATE(smlaw), - INTERPRETER_TRANSLATE(smulw), - INTERPRETER_TRANSLATE(pkhtb), - INTERPRETER_TRANSLATE(pkhbt), - INTERPRETER_TRANSLATE(smul), - INTERPRETER_TRANSLATE(smlalxy), - INTERPRETER_TRANSLATE(smla), - INTERPRETER_TRANSLATE(mcrr), - INTERPRETER_TRANSLATE(mrrc), - INTERPRETER_TRANSLATE(cmp), - INTERPRETER_TRANSLATE(tst), - INTERPRETER_TRANSLATE(teq), - INTERPRETER_TRANSLATE(cmn), - INTERPRETER_TRANSLATE(smull), - INTERPRETER_TRANSLATE(umull), - INTERPRETER_TRANSLATE(umlal), - INTERPRETER_TRANSLATE(smlal), - INTERPRETER_TRANSLATE(mul), - INTERPRETER_TRANSLATE(mla), - INTERPRETER_TRANSLATE(ssat), - INTERPRETER_TRANSLATE(usat), - INTERPRETER_TRANSLATE(mrs), - INTERPRETER_TRANSLATE(msr), - INTERPRETER_TRANSLATE(and), - INTERPRETER_TRANSLATE(bic), - INTERPRETER_TRANSLATE(ldm), - INTERPRETER_TRANSLATE(eor), - INTERPRETER_TRANSLATE(add), - INTERPRETER_TRANSLATE(rsb), - INTERPRETER_TRANSLATE(rsc), - INTERPRETER_TRANSLATE(sbc), - INTERPRETER_TRANSLATE(adc), - INTERPRETER_TRANSLATE(sub), - INTERPRETER_TRANSLATE(orr), - INTERPRETER_TRANSLATE(mvn), - INTERPRETER_TRANSLATE(mov), - INTERPRETER_TRANSLATE(stm), - INTERPRETER_TRANSLATE(ldm), - INTERPRETER_TRANSLATE(ldrsh), - INTERPRETER_TRANSLATE(stm), - INTERPRETER_TRANSLATE(ldm), - INTERPRETER_TRANSLATE(ldrsb), - INTERPRETER_TRANSLATE(strd), - INTERPRETER_TRANSLATE(ldrh), - INTERPRETER_TRANSLATE(strh), - INTERPRETER_TRANSLATE(ldrd), - INTERPRETER_TRANSLATE(strt), - INTERPRETER_TRANSLATE(strbt), - INTERPRETER_TRANSLATE(ldrbt), - INTERPRETER_TRANSLATE(ldrt), - INTERPRETER_TRANSLATE(mrc), - INTERPRETER_TRANSLATE(mcr), - INTERPRETER_TRANSLATE(msr), - INTERPRETER_TRANSLATE(msr), - INTERPRETER_TRANSLATE(msr), - INTERPRETER_TRANSLATE(msr), - INTERPRETER_TRANSLATE(msr), - INTERPRETER_TRANSLATE(ldrb), - INTERPRETER_TRANSLATE(strb), - INTERPRETER_TRANSLATE(ldr), - INTERPRETER_TRANSLATE(ldrcond), - INTERPRETER_TRANSLATE(str), - INTERPRETER_TRANSLATE(cdp), - INTERPRETER_TRANSLATE(stc), - INTERPRETER_TRANSLATE(ldc), - INTERPRETER_TRANSLATE(ldrexd), - INTERPRETER_TRANSLATE(strexd), - INTERPRETER_TRANSLATE(ldrexh), - INTERPRETER_TRANSLATE(strexh), - INTERPRETER_TRANSLATE(nop), - INTERPRETER_TRANSLATE(yield), - INTERPRETER_TRANSLATE(wfe), - INTERPRETER_TRANSLATE(wfi), - INTERPRETER_TRANSLATE(sev), - INTERPRETER_TRANSLATE(swi), + INTERPRETER_TRANSLATE(vmla), INTERPRETER_TRANSLATE(vmls), INTERPRETER_TRANSLATE(vnmla), + INTERPRETER_TRANSLATE(vnmls), INTERPRETER_TRANSLATE(vnmul), INTERPRETER_TRANSLATE(vmul), + INTERPRETER_TRANSLATE(vadd), INTERPRETER_TRANSLATE(vsub), INTERPRETER_TRANSLATE(vdiv), + INTERPRETER_TRANSLATE(vmovi), INTERPRETER_TRANSLATE(vmovr), INTERPRETER_TRANSLATE(vabs), + INTERPRETER_TRANSLATE(vneg), INTERPRETER_TRANSLATE(vsqrt), INTERPRETER_TRANSLATE(vcmp), + INTERPRETER_TRANSLATE(vcmp2), INTERPRETER_TRANSLATE(vcvtbds), INTERPRETER_TRANSLATE(vcvtbff), + INTERPRETER_TRANSLATE(vcvtbfi), INTERPRETER_TRANSLATE(vmovbrs), INTERPRETER_TRANSLATE(vmsr), + INTERPRETER_TRANSLATE(vmovbrc), INTERPRETER_TRANSLATE(vmrs), INTERPRETER_TRANSLATE(vmovbcr), + INTERPRETER_TRANSLATE(vmovbrrss), INTERPRETER_TRANSLATE(vmovbrrd), INTERPRETER_TRANSLATE(vstr), + INTERPRETER_TRANSLATE(vpush), INTERPRETER_TRANSLATE(vstm), INTERPRETER_TRANSLATE(vpop), + INTERPRETER_TRANSLATE(vldr), INTERPRETER_TRANSLATE(vldm), + + INTERPRETER_TRANSLATE(srs), INTERPRETER_TRANSLATE(rfe), INTERPRETER_TRANSLATE(bkpt), + INTERPRETER_TRANSLATE(blx), INTERPRETER_TRANSLATE(cps), INTERPRETER_TRANSLATE(pld), + INTERPRETER_TRANSLATE(setend), INTERPRETER_TRANSLATE(clrex), INTERPRETER_TRANSLATE(rev16), + INTERPRETER_TRANSLATE(usad8), INTERPRETER_TRANSLATE(sxtb), INTERPRETER_TRANSLATE(uxtb), + INTERPRETER_TRANSLATE(sxth), INTERPRETER_TRANSLATE(sxtb16), INTERPRETER_TRANSLATE(uxth), + INTERPRETER_TRANSLATE(uxtb16), INTERPRETER_TRANSLATE(cpy), INTERPRETER_TRANSLATE(uxtab), + INTERPRETER_TRANSLATE(ssub8), INTERPRETER_TRANSLATE(shsub8), INTERPRETER_TRANSLATE(ssubaddx), + INTERPRETER_TRANSLATE(strex), INTERPRETER_TRANSLATE(strexb), INTERPRETER_TRANSLATE(swp), + INTERPRETER_TRANSLATE(swpb), INTERPRETER_TRANSLATE(ssub16), INTERPRETER_TRANSLATE(ssat16), + INTERPRETER_TRANSLATE(shsubaddx), INTERPRETER_TRANSLATE(qsubaddx), + INTERPRETER_TRANSLATE(shaddsubx), INTERPRETER_TRANSLATE(shadd8), INTERPRETER_TRANSLATE(shadd16), + INTERPRETER_TRANSLATE(sel), INTERPRETER_TRANSLATE(saddsubx), INTERPRETER_TRANSLATE(sadd8), + INTERPRETER_TRANSLATE(sadd16), INTERPRETER_TRANSLATE(shsub16), INTERPRETER_TRANSLATE(umaal), + INTERPRETER_TRANSLATE(uxtab16), INTERPRETER_TRANSLATE(usubaddx), INTERPRETER_TRANSLATE(usub8), + INTERPRETER_TRANSLATE(usub16), INTERPRETER_TRANSLATE(usat16), INTERPRETER_TRANSLATE(usada8), + INTERPRETER_TRANSLATE(uqsubaddx), INTERPRETER_TRANSLATE(uqsub8), INTERPRETER_TRANSLATE(uqsub16), + INTERPRETER_TRANSLATE(uqaddsubx), INTERPRETER_TRANSLATE(uqadd8), INTERPRETER_TRANSLATE(uqadd16), + INTERPRETER_TRANSLATE(sxtab), INTERPRETER_TRANSLATE(uhsubaddx), INTERPRETER_TRANSLATE(uhsub8), + INTERPRETER_TRANSLATE(uhsub16), INTERPRETER_TRANSLATE(uhaddsubx), INTERPRETER_TRANSLATE(uhadd8), + INTERPRETER_TRANSLATE(uhadd16), INTERPRETER_TRANSLATE(uaddsubx), INTERPRETER_TRANSLATE(uadd8), + INTERPRETER_TRANSLATE(uadd16), INTERPRETER_TRANSLATE(sxtah), INTERPRETER_TRANSLATE(sxtab16), + INTERPRETER_TRANSLATE(qadd8), INTERPRETER_TRANSLATE(bxj), INTERPRETER_TRANSLATE(clz), + INTERPRETER_TRANSLATE(uxtah), INTERPRETER_TRANSLATE(bx), INTERPRETER_TRANSLATE(rev), + INTERPRETER_TRANSLATE(blx), INTERPRETER_TRANSLATE(revsh), INTERPRETER_TRANSLATE(qadd), + INTERPRETER_TRANSLATE(qadd16), INTERPRETER_TRANSLATE(qaddsubx), INTERPRETER_TRANSLATE(ldrex), + INTERPRETER_TRANSLATE(qdadd), INTERPRETER_TRANSLATE(qdsub), INTERPRETER_TRANSLATE(qsub), + INTERPRETER_TRANSLATE(ldrexb), INTERPRETER_TRANSLATE(qsub8), INTERPRETER_TRANSLATE(qsub16), + INTERPRETER_TRANSLATE(smuad), INTERPRETER_TRANSLATE(smmul), INTERPRETER_TRANSLATE(smusd), + INTERPRETER_TRANSLATE(smlsd), INTERPRETER_TRANSLATE(smlsld), INTERPRETER_TRANSLATE(smmla), + INTERPRETER_TRANSLATE(smmls), INTERPRETER_TRANSLATE(smlald), INTERPRETER_TRANSLATE(smlad), + INTERPRETER_TRANSLATE(smlaw), INTERPRETER_TRANSLATE(smulw), INTERPRETER_TRANSLATE(pkhtb), + INTERPRETER_TRANSLATE(pkhbt), INTERPRETER_TRANSLATE(smul), INTERPRETER_TRANSLATE(smlalxy), + INTERPRETER_TRANSLATE(smla), INTERPRETER_TRANSLATE(mcrr), INTERPRETER_TRANSLATE(mrrc), + INTERPRETER_TRANSLATE(cmp), INTERPRETER_TRANSLATE(tst), INTERPRETER_TRANSLATE(teq), + INTERPRETER_TRANSLATE(cmn), INTERPRETER_TRANSLATE(smull), INTERPRETER_TRANSLATE(umull), + INTERPRETER_TRANSLATE(umlal), INTERPRETER_TRANSLATE(smlal), INTERPRETER_TRANSLATE(mul), + INTERPRETER_TRANSLATE(mla), INTERPRETER_TRANSLATE(ssat), INTERPRETER_TRANSLATE(usat), + INTERPRETER_TRANSLATE(mrs), INTERPRETER_TRANSLATE(msr), INTERPRETER_TRANSLATE(and), + INTERPRETER_TRANSLATE(bic), INTERPRETER_TRANSLATE(ldm), INTERPRETER_TRANSLATE(eor), + INTERPRETER_TRANSLATE(add), INTERPRETER_TRANSLATE(rsb), INTERPRETER_TRANSLATE(rsc), + INTERPRETER_TRANSLATE(sbc), INTERPRETER_TRANSLATE(adc), INTERPRETER_TRANSLATE(sub), + INTERPRETER_TRANSLATE(orr), INTERPRETER_TRANSLATE(mvn), INTERPRETER_TRANSLATE(mov), + INTERPRETER_TRANSLATE(stm), INTERPRETER_TRANSLATE(ldm), INTERPRETER_TRANSLATE(ldrsh), + INTERPRETER_TRANSLATE(stm), INTERPRETER_TRANSLATE(ldm), INTERPRETER_TRANSLATE(ldrsb), + INTERPRETER_TRANSLATE(strd), INTERPRETER_TRANSLATE(ldrh), INTERPRETER_TRANSLATE(strh), + INTERPRETER_TRANSLATE(ldrd), INTERPRETER_TRANSLATE(strt), INTERPRETER_TRANSLATE(strbt), + INTERPRETER_TRANSLATE(ldrbt), INTERPRETER_TRANSLATE(ldrt), INTERPRETER_TRANSLATE(mrc), + INTERPRETER_TRANSLATE(mcr), INTERPRETER_TRANSLATE(msr), INTERPRETER_TRANSLATE(msr), + INTERPRETER_TRANSLATE(msr), INTERPRETER_TRANSLATE(msr), INTERPRETER_TRANSLATE(msr), + INTERPRETER_TRANSLATE(ldrb), INTERPRETER_TRANSLATE(strb), INTERPRETER_TRANSLATE(ldr), + INTERPRETER_TRANSLATE(ldrcond), INTERPRETER_TRANSLATE(str), INTERPRETER_TRANSLATE(cdp), + INTERPRETER_TRANSLATE(stc), INTERPRETER_TRANSLATE(ldc), INTERPRETER_TRANSLATE(ldrexd), + INTERPRETER_TRANSLATE(strexd), INTERPRETER_TRANSLATE(ldrexh), INTERPRETER_TRANSLATE(strexh), + INTERPRETER_TRANSLATE(nop), INTERPRETER_TRANSLATE(yield), INTERPRETER_TRANSLATE(wfe), + INTERPRETER_TRANSLATE(wfi), INTERPRETER_TRANSLATE(sev), INTERPRETER_TRANSLATE(swi), INTERPRETER_TRANSLATE(bbl), // All the thumb instructions should be placed the end of table - INTERPRETER_TRANSLATE(b_2_thumb), - INTERPRETER_TRANSLATE(b_cond_thumb), - INTERPRETER_TRANSLATE(bl_1_thumb), - INTERPRETER_TRANSLATE(bl_2_thumb), - INTERPRETER_TRANSLATE(blx_1_thumb) -}; + INTERPRETER_TRANSLATE(b_2_thumb), INTERPRETER_TRANSLATE(b_cond_thumb), + INTERPRETER_TRANSLATE(bl_1_thumb), INTERPRETER_TRANSLATE(bl_2_thumb), + INTERPRETER_TRANSLATE(blx_1_thumb)}; const size_t arm_instruction_trans_len = sizeof(arm_instruction_trans) / sizeof(transop_fp_t); diff --git a/src/core/arm/dyncom/arm_dyncom_trans.h b/src/core/arm/dyncom/arm_dyncom_trans.h index 7af71f4e3..6fdb3d248 100644 --- a/src/core/arm/dyncom/arm_dyncom_trans.h +++ b/src/core/arm/dyncom/arm_dyncom_trans.h @@ -2,15 +2,15 @@ struct ARMul_State; typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper); enum class TransExtData { - COND = (1 << 0), - NON_BRANCH = (1 << 1), - DIRECT_BRANCH = (1 << 2), + COND = (1 << 0), + NON_BRANCH = (1 << 1), + DIRECT_BRANCH = (1 << 2), INDIRECT_BRANCH = (1 << 3), - CALL = (1 << 4), - RET = (1 << 5), - END_OF_PAGE = (1 << 6), - THUMB = (1 << 7), - SINGLE_STEP = (1 << 8) + CALL = (1 << 4), + RET = (1 << 5), + END_OF_PAGE = (1 << 6), + THUMB = (1 << 7), + SINGLE_STEP = (1 << 8) }; struct arm_inst { @@ -106,8 +106,7 @@ struct cps_inst { unsigned int mode; }; -struct clrex_inst { -}; +struct clrex_inst {}; struct cpy_inst { unsigned int Rm; @@ -163,11 +162,9 @@ struct bkpt_inst { u32 imm; }; -struct stc_inst { -}; +struct stc_inst {}; -struct ldc_inst { -}; +struct ldc_inst {}; struct swi_inst { unsigned int num; @@ -369,8 +366,7 @@ struct msr_inst { unsigned int inst; }; -struct pld_inst { -}; +struct pld_inst {}; struct sxtb_inst { unsigned int Rd; @@ -475,7 +471,7 @@ struct pkh_inst { #include "core/arm/skyeye_common/vfp/vfpinstr.cpp" #undef VFP_INTERPRETER_STRUCT -typedef void (*get_addr_fp_t)(ARMul_State *cpu, unsigned int inst, unsigned int &virt_addr); +typedef void (*get_addr_fp_t)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr); struct ldst_inst { unsigned int inst; diff --git a/src/core/arm/skyeye_common/arm_regformat.h b/src/core/arm/skyeye_common/arm_regformat.h index 38fa97ab9..706195a05 100644 --- a/src/core/arm/skyeye_common/arm_regformat.h +++ b/src/core/arm/skyeye_common/arm_regformat.h @@ -16,7 +16,7 @@ enum { R12, R13, LR, - R15, //PC, + R15, // PC, CPSR_REG, SPSR_REG, diff --git a/src/core/arm/skyeye_common/armstate.cpp b/src/core/arm/skyeye_common/armstate.cpp index 5550c112e..59329c656 100644 --- a/src/core/arm/skyeye_common/armstate.cpp +++ b/src/core/arm/skyeye_common/armstate.cpp @@ -2,22 +2,20 @@ // Licensed under GPLv2 or any later version // Refer to the license.txt file included. +#include "core/arm/skyeye_common/armstate.h" #include <algorithm> -#include "common/swap.h" #include "common/logging/log.h" -#include "core/memory.h" -#include "core/arm/skyeye_common/armstate.h" +#include "common/swap.h" #include "core/arm/skyeye_common/vfp/vfp.h" #include "core/gdbstub/gdbstub.h" +#include "core/memory.h" -ARMul_State::ARMul_State(PrivilegeMode initial_mode) -{ +ARMul_State::ARMul_State(PrivilegeMode initial_mode) { Reset(); ChangePrivilegeMode(initial_mode); } -void ARMul_State::ChangePrivilegeMode(u32 new_mode) -{ +void ARMul_State::ChangePrivilegeMode(u32 new_mode) { if (Mode == new_mode) return; @@ -103,8 +101,7 @@ void ARMul_State::ChangePrivilegeMode(u32 new_mode) } // Performs a reset -void ARMul_State::Reset() -{ +void ARMul_State::Reset() { VFPInit(this); // Set stack pointer to the top of the stack @@ -128,8 +125,7 @@ void ARMul_State::Reset() } // Resets certain MPCore CP15 values to their ARM-defined reset values. -void ARMul_State::ResetMPCoreCP15Registers() -{ +void ARMul_State::ResetMPCoreCP15Registers() { // c0 CP15[CP15_MAIN_ID] = 0x410FB024; CP15[CP15_TLB_TYPE] = 0x00000800; @@ -185,23 +181,20 @@ void ARMul_State::ResetMPCoreCP15Registers() CP15[CP15_TLB_DEBUG_CONTROL] = 0x00000000; } -static void CheckMemoryBreakpoint(u32 address, GDBStub::BreakpointType type) -{ +static void CheckMemoryBreakpoint(u32 address, GDBStub::BreakpointType type) { if (GDBStub::g_server_enabled && GDBStub::CheckBreakpoint(address, type)) { LOG_DEBUG(Debug, "Found memory breakpoint @ %08x", address); GDBStub::Break(true); } } -u8 ARMul_State::ReadMemory8(u32 address) const -{ +u8 ARMul_State::ReadMemory8(u32 address) const { CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Read); return Memory::Read8(address); } -u16 ARMul_State::ReadMemory16(u32 address) const -{ +u16 ARMul_State::ReadMemory16(u32 address) const { CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Read); u16 data = Memory::Read16(address); @@ -212,8 +205,7 @@ u16 ARMul_State::ReadMemory16(u32 address) const return data; } -u32 ARMul_State::ReadMemory32(u32 address) const -{ +u32 ARMul_State::ReadMemory32(u32 address) const { CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Read); u32 data = Memory::Read32(address); @@ -224,8 +216,7 @@ u32 ARMul_State::ReadMemory32(u32 address) const return data; } -u64 ARMul_State::ReadMemory64(u32 address) const -{ +u64 ARMul_State::ReadMemory64(u32 address) const { CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Read); u64 data = Memory::Read64(address); @@ -236,15 +227,13 @@ u64 ARMul_State::ReadMemory64(u32 address) const return data; } -void ARMul_State::WriteMemory8(u32 address, u8 data) -{ +void ARMul_State::WriteMemory8(u32 address, u8 data) { CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Write); Memory::Write8(address, data); } -void ARMul_State::WriteMemory16(u32 address, u16 data) -{ +void ARMul_State::WriteMemory16(u32 address, u16 data) { CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Write); if (InBigEndianMode()) @@ -253,8 +242,7 @@ void ARMul_State::WriteMemory16(u32 address, u16 data) Memory::Write16(address, data); } -void ARMul_State::WriteMemory32(u32 address, u32 data) -{ +void ARMul_State::WriteMemory32(u32 address, u32 data) { CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Write); if (InBigEndianMode()) @@ -263,8 +251,7 @@ void ARMul_State::WriteMemory32(u32 address, u32 data) Memory::Write32(address, data); } -void ARMul_State::WriteMemory64(u32 address, u64 data) -{ +void ARMul_State::WriteMemory64(u32 address, u64 data) { CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Write); if (InBigEndianMode()) @@ -273,15 +260,12 @@ void ARMul_State::WriteMemory64(u32 address, u64 data) Memory::Write64(address, data); } - // Reads from the CP15 registers. Used with implementation of the MRC instruction. // Note that since the 3DS does not have the hypervisor extensions, these registers // are not implemented. -u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) const -{ +u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) const { // Unprivileged registers - if (crn == 13 && opcode_1 == 0 && crm == 0) - { + if (crn == 13 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 2) return CP15[CP15_THREAD_UPRW]; @@ -289,12 +273,9 @@ u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) return CP15[CP15_THREAD_URO]; } - if (InAPrivilegedMode()) - { - if (crn == 0 && opcode_1 == 0) - { - if (crm == 0) - { + if (InAPrivilegedMode()) { + if (crn == 0 && opcode_1 == 0) { + if (crm == 0) { if (opcode_2 == 0) return CP15[CP15_MAIN_ID]; @@ -306,9 +287,7 @@ u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) if (opcode_2 == 5) return CP15[CP15_CPU_ID]; - } - else if (crm == 1) - { + } else if (crm == 1) { if (opcode_2 == 0) return CP15[CP15_PROCESSOR_FEATURE_0]; @@ -329,9 +308,7 @@ u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) if (opcode_2 == 7) return CP15[CP15_MEMORY_MODEL_FEATURE_3]; - } - else if (crm == 2) - { + } else if (crm == 2) { if (opcode_2 == 0) return CP15[CP15_ISA_FEATURE_0]; @@ -349,8 +326,7 @@ u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) } } - if (crn == 1 && opcode_1 == 0 && crm == 0) - { + if (crn == 1 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) return CP15[CP15_CONTROL]; @@ -361,8 +337,7 @@ u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) return CP15[CP15_COPROCESSOR_ACCESS_CONTROL]; } - if (crn == 2 && opcode_1 == 0 && crm == 0) - { + if (crn == 2 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) return CP15[CP15_TRANSLATION_BASE_TABLE_0]; @@ -376,8 +351,7 @@ u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) return CP15[CP15_DOMAIN_ACCESS_CONTROL]; - if (crn == 5 && opcode_1 == 0 && crm == 0) - { + if (crn == 5 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) return CP15[CP15_FAULT_STATUS]; @@ -385,8 +359,7 @@ u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) return CP15[CP15_INSTR_FAULT_STATUS]; } - if (crn == 6 && opcode_1 == 0 && crm == 0) - { + if (crn == 6 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) return CP15[CP15_FAULT_ADDRESS]; @@ -400,13 +373,11 @@ u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) return CP15[CP15_DATA_CACHE_LOCKDOWN]; - if (crn == 10 && opcode_1 == 0) - { + if (crn == 10 && opcode_1 == 0) { if (crm == 0 && opcode_2 == 0) return CP15[CP15_TLB_LOCKDOWN]; - if (crm == 2) - { + if (crm == 2) { if (opcode_2 == 0) return CP15[CP15_PRIMARY_REGION_REMAP]; @@ -415,8 +386,7 @@ u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) } } - if (crn == 13 && crm == 0) - { + if (crn == 13 && crm == 0) { if (opcode_2 == 0) return CP15[CP15_PID]; @@ -427,10 +397,8 @@ u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) return CP15[CP15_THREAD_PRW]; } - if (crn == 15) - { - if (opcode_1 == 0 && crm == 12) - { + if (crn == 15) { + if (opcode_1 == 0 && crm == 12) { if (opcode_2 == 0) return CP15[CP15_PERFORMANCE_MONITOR_CONTROL]; @@ -444,8 +412,7 @@ u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) return CP15[CP15_COUNT_1]; } - if (opcode_1 == 5 && opcode_2 == 2) - { + if (opcode_1 == 5 && opcode_2 == 2) { if (crm == 5) return CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS]; @@ -461,66 +428,49 @@ u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) } } - LOG_ERROR(Core_ARM11, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", crn, crm, opcode_1, opcode_2); + LOG_ERROR(Core_ARM11, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", + crn, crm, opcode_1, opcode_2); return 0; } // Write to the CP15 registers. Used with implementation of the MCR instruction. // Note that since the 3DS does not have the hypervisor extensions, these registers // are not implemented. -void ARMul_State::WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) -{ - if (InAPrivilegedMode()) - { - if (crn == 1 && opcode_1 == 0 && crm == 0) - { +void ARMul_State::WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) { + if (InAPrivilegedMode()) { + if (crn == 1 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) CP15[CP15_CONTROL] = value; else if (opcode_2 == 1) CP15[CP15_AUXILIARY_CONTROL] = value; else if (opcode_2 == 2) CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = value; - } - else if (crn == 2 && opcode_1 == 0 && crm == 0) - { + } else if (crn == 2 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) CP15[CP15_TRANSLATION_BASE_TABLE_0] = value; else if (opcode_2 == 1) CP15[CP15_TRANSLATION_BASE_TABLE_1] = value; else if (opcode_2 == 2) CP15[CP15_TRANSLATION_BASE_CONTROL] = value; - } - else if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) - { + } else if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) { CP15[CP15_DOMAIN_ACCESS_CONTROL] = value; - } - else if (crn == 5 && opcode_1 == 0 && crm == 0) - { + } else if (crn == 5 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) CP15[CP15_FAULT_STATUS] = value; else if (opcode_2 == 1) CP15[CP15_INSTR_FAULT_STATUS] = value; - } - else if (crn == 6 && opcode_1 == 0 && crm == 0) - { + } else if (crn == 6 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) CP15[CP15_FAULT_ADDRESS] = value; else if (opcode_2 == 1) CP15[CP15_WFAR] = value; - } - else if (crn == 7 && opcode_1 == 0) - { - if (crm == 0 && opcode_2 == 4) - { + } else if (crn == 7 && opcode_1 == 0) { + if (crm == 0 && opcode_2 == 4) { CP15[CP15_WAIT_FOR_INTERRUPT] = value; - } - else if (crm == 4 && opcode_2 == 0) - { + } else if (crm == 4 && opcode_2 == 0) { // NOTE: Not entirely accurate. This should do permission checks. CP15[CP15_PHYS_ADDRESS] = Memory::VirtualToPhysicalAddress(value); - } - else if (crm == 5) - { + } else if (crm == 5) { if (opcode_2 == 0) CP15[CP15_INVALIDATE_INSTR_CACHE] = value; else if (opcode_2 == 1) @@ -531,31 +481,23 @@ void ARMul_State::WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u CP15[CP15_FLUSH_BRANCH_TARGET_CACHE] = value; else if (opcode_2 == 7) CP15[CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY] = value; - } - else if (crm == 6) - { + } else if (crm == 6) { if (opcode_2 == 0) CP15[CP15_INVALIDATE_DATA_CACHE] = value; else if (opcode_2 == 1) CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA] = value; else if (opcode_2 == 2) CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value; - } - else if (crm == 7 && opcode_2 == 0) - { + } else if (crm == 7 && opcode_2 == 0) { CP15[CP15_INVALIDATE_DATA_AND_INSTR_CACHE] = value; - } - else if (crm == 10) - { + } else if (crm == 10) { if (opcode_2 == 0) CP15[CP15_CLEAN_DATA_CACHE] = value; else if (opcode_2 == 1) CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_MVA] = value; else if (opcode_2 == 2) CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX] = value; - } - else if (crm == 14) - { + } else if (crm == 14) { if (opcode_2 == 0) CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE] = value; else if (opcode_2 == 1) @@ -563,11 +505,8 @@ void ARMul_State::WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u else if (opcode_2 == 2) CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value; } - } - else if (crn == 8 && opcode_1 == 0) - { - if (crm == 5) - { + } else if (crn == 8 && opcode_1 == 0) { + if (crm == 5) { if (opcode_2 == 0) CP15[CP15_INVALIDATE_ITLB] = value; else if (opcode_2 == 1) @@ -576,9 +515,7 @@ void ARMul_State::WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH] = value; else if (opcode_2 == 3) CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_MVA] = value; - } - else if (crm == 6) - { + } else if (crm == 6) { if (opcode_2 == 0) CP15[CP15_INVALIDATE_DTLB] = value; else if (opcode_2 == 1) @@ -587,9 +524,7 @@ void ARMul_State::WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH] = value; else if (opcode_2 == 3) CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_MVA] = value; - } - else if (crm == 7) - { + } else if (crm == 7) { if (opcode_2 == 0) CP15[CP15_INVALIDATE_UTLB] = value; else if (opcode_2 == 1) @@ -599,27 +534,18 @@ void ARMul_State::WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u else if (opcode_2 == 3) CP15[CP15_INVALIDATE_UTLB_ENTRY_ON_MVA] = value; } - } - else if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) - { + } else if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) { CP15[CP15_DATA_CACHE_LOCKDOWN] = value; - } - else if (crn == 10 && opcode_1 == 0) - { - if (crm == 0 && opcode_2 == 0) - { + } else if (crn == 10 && opcode_1 == 0) { + if (crm == 0 && opcode_2 == 0) { CP15[CP15_TLB_LOCKDOWN] = value; - } - else if (crm == 2) - { + } else if (crm == 2) { if (opcode_2 == 0) CP15[CP15_PRIMARY_REGION_REMAP] = value; else if (opcode_2 == 1) CP15[CP15_NORMAL_REGION_REMAP] = value; } - } - else if (crn == 13 && opcode_1 == 0 && crm == 0) - { + } else if (crn == 13 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) CP15[CP15_PID] = value; else if (opcode_2 == 1) @@ -628,11 +554,8 @@ void ARMul_State::WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u CP15[CP15_THREAD_URO] = value; else if (opcode_2 == 4) CP15[CP15_THREAD_PRW] = value; - } - else if (crn == 15) - { - if (opcode_1 == 0 && crm == 12) - { + } else if (crn == 15) { + if (opcode_1 == 0 && crm == 12) { if (opcode_2 == 0) CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = value; else if (opcode_2 == 1) @@ -641,50 +564,34 @@ void ARMul_State::WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u CP15[CP15_COUNT_0] = value; else if (opcode_2 == 3) CP15[CP15_COUNT_1] = value; - } - else if (opcode_1 == 5) - { - if (crm == 4) - { + } else if (opcode_1 == 5) { + if (crm == 4) { if (opcode_2 == 2) CP15[CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY] = value; else if (opcode_2 == 4) CP15[CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY] = value; - } - else if (crm == 5 && opcode_2 == 2) - { + } else if (crm == 5 && opcode_2 == 2) { CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = value; - } - else if (crm == 6 && opcode_2 == 2) - { + } else if (crm == 6 && opcode_2 == 2) { CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = value; - } - else if (crm == 7 && opcode_2 == 2) - { + } else if (crm == 7 && opcode_2 == 2) { CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = value; } - } - else if (opcode_1 == 7 && crm == 1 && opcode_2 == 0) - { + } else if (opcode_1 == 7 && crm == 1 && opcode_2 == 0) { CP15[CP15_TLB_DEBUG_CONTROL] = value; } } } // Unprivileged registers - if (crn == 7 && opcode_1 == 0 && crm == 5 && opcode_2 == 4) - { + if (crn == 7 && opcode_1 == 0 && crm == 5 && opcode_2 == 4) { CP15[CP15_FLUSH_PREFETCH_BUFFER] = value; - } - else if (crn == 7 && opcode_1 == 0 && crm == 10) - { + } else if (crn == 7 && opcode_1 == 0 && crm == 10) { if (opcode_2 == 4) CP15[CP15_DATA_SYNC_BARRIER] = value; else if (opcode_2 == 5) CP15[CP15_DATA_MEMORY_BARRIER] = value; - } - else if (crn == 13 && opcode_1 == 0 && crm == 0 && opcode_2 == 2) - { + } else if (crn == 13 && opcode_1 == 0 && crm == 0 && opcode_2 == 2) { CP15[CP15_THREAD_UPRW] = value; } } diff --git a/src/core/arm/skyeye_common/armstate.h b/src/core/arm/skyeye_common/armstate.h index d42ff2669..66567c285 100644 --- a/src/core/arm/skyeye_common/armstate.h +++ b/src/core/arm/skyeye_common/armstate.h @@ -24,75 +24,70 @@ #include "core/arm/skyeye_common/arm_regformat.h" // Signal levels -enum { - LOW = 0, - HIGH = 1, - LOWHIGH = 1, - HIGHLOW = 2 -}; +enum { LOW = 0, HIGH = 1, LOWHIGH = 1, HIGHLOW = 2 }; // Cache types enum { - NONCACHE = 0, + NONCACHE = 0, DATACACHE = 1, INSTCACHE = 2, }; // ARM privilege modes enum PrivilegeMode { - USER32MODE = 16, - FIQ32MODE = 17, - IRQ32MODE = 18, - SVC32MODE = 19, - ABORT32MODE = 23, - UNDEF32MODE = 27, + USER32MODE = 16, + FIQ32MODE = 17, + IRQ32MODE = 18, + SVC32MODE = 19, + ABORT32MODE = 23, + UNDEF32MODE = 27, SYSTEM32MODE = 31 }; // ARM privilege mode register banks enum { - USERBANK = 0, - FIQBANK = 1, - IRQBANK = 2, - SVCBANK = 3, - ABORTBANK = 4, - UNDEFBANK = 5, - DUMMYBANK = 6, + USERBANK = 0, + FIQBANK = 1, + IRQBANK = 2, + SVCBANK = 3, + ABORTBANK = 4, + UNDEFBANK = 5, + DUMMYBANK = 6, SYSTEMBANK = 7 }; // Hardware vector addresses enum { - ARMResetV = 0, + ARMResetV = 0, ARMUndefinedInstrV = 4, - ARMSWIV = 8, - ARMPrefetchAbortV = 12, - ARMDataAbortV = 16, - ARMAddrExceptnV = 20, - ARMIRQV = 24, - ARMFIQV = 28, - ARMErrorV = 32, // This is an offset, not an address! - - ARMul_ResetV = ARMResetV, + ARMSWIV = 8, + ARMPrefetchAbortV = 12, + ARMDataAbortV = 16, + ARMAddrExceptnV = 20, + ARMIRQV = 24, + ARMFIQV = 28, + ARMErrorV = 32, // This is an offset, not an address! + + ARMul_ResetV = ARMResetV, ARMul_UndefinedInstrV = ARMUndefinedInstrV, - ARMul_SWIV = ARMSWIV, - ARMul_PrefetchAbortV = ARMPrefetchAbortV, - ARMul_DataAbortV = ARMDataAbortV, - ARMul_AddrExceptnV = ARMAddrExceptnV, - ARMul_IRQV = ARMIRQV, - ARMul_FIQV = ARMFIQV + ARMul_SWIV = ARMSWIV, + ARMul_PrefetchAbortV = ARMPrefetchAbortV, + ARMul_DataAbortV = ARMDataAbortV, + ARMul_AddrExceptnV = ARMAddrExceptnV, + ARMul_IRQV = ARMIRQV, + ARMul_FIQV = ARMFIQV }; // Coprocessor status values enum { - ARMul_FIRST = 0, - ARMul_TRANSFER = 1, - ARMul_BUSY = 2, - ARMul_DATA = 3, + ARMul_FIRST = 0, + ARMul_TRANSFER = 1, + ARMul_BUSY = 2, + ARMul_DATA = 3, ARMul_INTERRUPT = 4, - ARMul_DONE = 0, - ARMul_CANT = 1, - ARMul_INC = 3 + ARMul_DONE = 0, + ARMul_CANT = 1, + ARMul_INC = 3 }; // Instruction condition codes @@ -136,15 +131,13 @@ enum : u32 { // Values for Emulate. enum { - STOP = 0, // Stop + STOP = 0, // Stop CHANGEMODE = 1, // Change mode - ONCE = 2, // Execute just one iteration - RUN = 3 // Continuous execution + ONCE = 2, // Execute just one iteration + RUN = 3 // Continuous execution }; - -struct ARMul_State final -{ +struct ARMul_State final { public: explicit ARMul_State(PrivilegeMode initial_mode); @@ -193,7 +186,7 @@ public: return TFlag ? 2 : 4; } - std::array<u32, 16> Reg{}; // The current register file + std::array<u32, 16> Reg{}; // The current register file std::array<u32, 2> Reg_usr{}; std::array<u32, 2> Reg_svc{}; // R13_SVC R14_SVC std::array<u32, 2> Reg_abort{}; // R13_ABORT R14_ABORT @@ -216,8 +209,8 @@ public: u32 Spsr_copy; u32 phys_pc; - u32 Mode; // The current mode - u32 Bank; // The current register bank + u32 Mode; // The current mode + u32 Bank; // The current register bank u32 NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed unsigned int shifter_carry_out; @@ -243,8 +236,10 @@ public: private: void ResetMPCoreCP15Registers(); - // Defines a reservation granule of 2 words, which protects the first 2 words starting at the tag. - // This is the smallest granule allowed by the v7 spec, and is coincidentally just large enough to + // Defines a reservation granule of 2 words, which protects the first 2 words starting at the + // tag. + // This is the smallest granule allowed by the v7 spec, and is coincidentally just large enough + // to // support LDR/STREXD. static const u32 RESERVATION_GRANULE_MASK = 0xFFFFFFF8; diff --git a/src/core/arm/skyeye_common/armsupp.cpp b/src/core/arm/skyeye_common/armsupp.cpp index 883713e86..e70be29a7 100644 --- a/src/core/arm/skyeye_common/armsupp.cpp +++ b/src/core/arm/skyeye_common/armsupp.cpp @@ -22,8 +22,7 @@ #include "core/arm/skyeye_common/armsupp.h" // Unsigned sum of absolute difference -u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right) -{ +u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right) { if (left > right) return left - right; @@ -31,8 +30,8 @@ u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right) } // Add with carry, indicates if a carry-out or signed overflow occurred. -u32 AddWithCarry(u32 left, u32 right, u32 carry_in, bool* carry_out_occurred, bool* overflow_occurred) -{ +u32 AddWithCarry(u32 left, u32 right, u32 carry_in, bool* carry_out_occurred, + bool* overflow_occurred) { u64 unsigned_sum = (u64)left + (u64)right + (u64)carry_in; s64 signed_sum = (s64)(s32)left + (s64)(s32)right + (s64)carry_in; u64 result = (unsigned_sum & 0xFFFFFFFF); @@ -47,22 +46,17 @@ u32 AddWithCarry(u32 left, u32 right, u32 carry_in, bool* carry_out_occurred, bo } // Compute whether an addition of A and B, giving RESULT, overflowed. -bool AddOverflow(u32 a, u32 b, u32 result) -{ - return ((NEG(a) && NEG(b) && POS(result)) || - (POS(a) && POS(b) && NEG(result))); +bool AddOverflow(u32 a, u32 b, u32 result) { + return ((NEG(a) && NEG(b) && POS(result)) || (POS(a) && POS(b) && NEG(result))); } // Compute whether a subtraction of A and B, giving RESULT, overflowed. -bool SubOverflow(u32 a, u32 b, u32 result) -{ - return ((NEG(a) && POS(b) && POS(result)) || - (POS(a) && NEG(b) && NEG(result))); +bool SubOverflow(u32 a, u32 b, u32 result) { + return ((NEG(a) && POS(b) && POS(result)) || (POS(a) && NEG(b) && NEG(result))); } // Returns true if the Q flag should be set as a result of overflow. -bool ARMul_AddOverflowQ(u32 a, u32 b) -{ +bool ARMul_AddOverflowQ(u32 a, u32 b) { u32 result = a + b; if (((result ^ a) & (u32)0x80000000) && ((a ^ b) & (u32)0x80000000) == 0) return true; @@ -71,8 +65,7 @@ bool ARMul_AddOverflowQ(u32 a, u32 b) } // 8-bit signed saturated addition -u8 ARMul_SignedSaturatedAdd8(u8 left, u8 right) -{ +u8 ARMul_SignedSaturatedAdd8(u8 left, u8 right) { u8 result = left + right; if (((result ^ left) & 0x80) && ((left ^ right) & 0x80) == 0) { @@ -86,8 +79,7 @@ u8 ARMul_SignedSaturatedAdd8(u8 left, u8 right) } // 8-bit signed saturated subtraction -u8 ARMul_SignedSaturatedSub8(u8 left, u8 right) -{ +u8 ARMul_SignedSaturatedSub8(u8 left, u8 right) { u8 result = left - right; if (((result ^ left) & 0x80) && ((left ^ right) & 0x80) != 0) { @@ -101,8 +93,7 @@ u8 ARMul_SignedSaturatedSub8(u8 left, u8 right) } // 16-bit signed saturated addition -u16 ARMul_SignedSaturatedAdd16(u16 left, u16 right) -{ +u16 ARMul_SignedSaturatedAdd16(u16 left, u16 right) { u16 result = left + right; if (((result ^ left) & 0x8000) && ((left ^ right) & 0x8000) == 0) { @@ -116,8 +107,7 @@ u16 ARMul_SignedSaturatedAdd16(u16 left, u16 right) } // 16-bit signed saturated subtraction -u16 ARMul_SignedSaturatedSub16(u16 left, u16 right) -{ +u16 ARMul_SignedSaturatedSub16(u16 left, u16 right) { u16 result = left - right; if (((result ^ left) & 0x8000) && ((left ^ right) & 0x8000) != 0) { @@ -131,8 +121,7 @@ u16 ARMul_SignedSaturatedSub16(u16 left, u16 right) } // 8-bit unsigned saturated addition -u8 ARMul_UnsignedSaturatedAdd8(u8 left, u8 right) -{ +u8 ARMul_UnsignedSaturatedAdd8(u8 left, u8 right) { u8 result = left + right; if (result < left) @@ -142,8 +131,7 @@ u8 ARMul_UnsignedSaturatedAdd8(u8 left, u8 right) } // 16-bit unsigned saturated addition -u16 ARMul_UnsignedSaturatedAdd16(u16 left, u16 right) -{ +u16 ARMul_UnsignedSaturatedAdd16(u16 left, u16 right) { u16 result = left + right; if (result < left) @@ -153,8 +141,7 @@ u16 ARMul_UnsignedSaturatedAdd16(u16 left, u16 right) } // 8-bit unsigned saturated subtraction -u8 ARMul_UnsignedSaturatedSub8(u8 left, u8 right) -{ +u8 ARMul_UnsignedSaturatedSub8(u8 left, u8 right) { if (left <= right) return 0; @@ -162,8 +149,7 @@ u8 ARMul_UnsignedSaturatedSub8(u8 left, u8 right) } // 16-bit unsigned saturated subtraction -u16 ARMul_UnsignedSaturatedSub16(u16 left, u16 right) -{ +u16 ARMul_UnsignedSaturatedSub16(u16 left, u16 right) { if (left <= right) return 0; @@ -171,16 +157,14 @@ u16 ARMul_UnsignedSaturatedSub16(u16 left, u16 right) } // Signed saturation. -u32 ARMul_SignedSatQ(s32 value, u8 shift, bool* saturation_occurred) -{ +u32 ARMul_SignedSatQ(s32 value, u8 shift, bool* saturation_occurred) { const u32 max = (1 << shift) - 1; const s32 top = (value >> shift); if (top > 0) { *saturation_occurred = true; return max; - } - else if (top < -1) { + } else if (top < -1) { *saturation_occurred = true; return ~max; } @@ -190,8 +174,7 @@ u32 ARMul_SignedSatQ(s32 value, u8 shift, bool* saturation_occurred) } // Unsigned saturation -u32 ARMul_UnsignedSatQ(s32 value, u8 shift, bool* saturation_occurred) -{ +u32 ARMul_UnsignedSatQ(s32 value, u8 shift, bool* saturation_occurred) { const u32 max = (1 << shift) - 1; if (value < 0) { diff --git a/src/core/arm/skyeye_common/armsupp.h b/src/core/arm/skyeye_common/armsupp.h index 391309fa8..bf9299c07 100644 --- a/src/core/arm/skyeye_common/armsupp.h +++ b/src/core/arm/skyeye_common/armsupp.h @@ -9,8 +9,8 @@ #define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1)) #define BIT(s, n) ((s >> (n)) & 1) -#define POS(i) ( (~(i)) >> 31 ) -#define NEG(i) ( (i) >> 31 ) +#define POS(i) ((~(i)) >> 31) +#define NEG(i) ((i) >> 31) bool AddOverflow(u32, u32, u32); bool SubOverflow(u32, u32, u32); diff --git a/src/core/arm/skyeye_common/vfp/asm_vfp.h b/src/core/arm/skyeye_common/vfp/asm_vfp.h index 1187924f4..15b2394eb 100644 --- a/src/core/arm/skyeye_common/vfp/asm_vfp.h +++ b/src/core/arm/skyeye_common/vfp/asm_vfp.h @@ -10,74 +10,74 @@ // ARM11 MPCore FPSID Information // Note that these are used as values and not as flags. enum : u32 { - VFP_FPSID_IMPLMEN = 0x41, // Implementation code. Should be the same as cp15 0 c0 0 - VFP_FPSID_SW = 0, // Software emulation bit value - VFP_FPSID_SUBARCH = 0x1, // Subarchitecture version number - VFP_FPSID_PARTNUM = 0x20, // Part number - VFP_FPSID_VARIANT = 0xB, // Variant number - VFP_FPSID_REVISION = 0x4 // Revision number + VFP_FPSID_IMPLMEN = 0x41, // Implementation code. Should be the same as cp15 0 c0 0 + VFP_FPSID_SW = 0, // Software emulation bit value + VFP_FPSID_SUBARCH = 0x1, // Subarchitecture version number + VFP_FPSID_PARTNUM = 0x20, // Part number + VFP_FPSID_VARIANT = 0xB, // Variant number + VFP_FPSID_REVISION = 0x4 // Revision number }; // FPEXC bits enum : u32 { - FPEXC_EX = (1U << 31U), - FPEXC_EN = (1 << 30), - FPEXC_DEX = (1 << 29), - FPEXC_FP2V = (1 << 28), - FPEXC_VV = (1 << 27), - FPEXC_TFV = (1 << 26), - FPEXC_LENGTH_BIT = (8), + FPEXC_EX = (1U << 31U), + FPEXC_EN = (1 << 30), + FPEXC_DEX = (1 << 29), + FPEXC_FP2V = (1 << 28), + FPEXC_VV = (1 << 27), + FPEXC_TFV = (1 << 26), + FPEXC_LENGTH_BIT = (8), FPEXC_LENGTH_MASK = (7 << FPEXC_LENGTH_BIT), - FPEXC_IDF = (1 << 7), - FPEXC_IXF = (1 << 4), - FPEXC_UFF = (1 << 3), - FPEXC_OFF = (1 << 2), - FPEXC_DZF = (1 << 1), - FPEXC_IOF = (1 << 0), - FPEXC_TRAP_MASK = (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF) + FPEXC_IDF = (1 << 7), + FPEXC_IXF = (1 << 4), + FPEXC_UFF = (1 << 3), + FPEXC_OFF = (1 << 2), + FPEXC_DZF = (1 << 1), + FPEXC_IOF = (1 << 0), + FPEXC_TRAP_MASK = (FPEXC_IDF | FPEXC_IXF | FPEXC_UFF | FPEXC_OFF | FPEXC_DZF | FPEXC_IOF) }; // FPSCR Flags enum : u32 { - FPSCR_NFLAG = (1U << 31U), // Negative condition flag - FPSCR_ZFLAG = (1 << 30), // Zero condition flag - FPSCR_CFLAG = (1 << 29), // Carry condition flag - FPSCR_VFLAG = (1 << 28), // Overflow condition flag + FPSCR_NFLAG = (1U << 31U), // Negative condition flag + FPSCR_ZFLAG = (1 << 30), // Zero condition flag + FPSCR_CFLAG = (1 << 29), // Carry condition flag + FPSCR_VFLAG = (1 << 28), // Overflow condition flag - FPSCR_QC = (1 << 27), // Cumulative saturation bit - FPSCR_AHP = (1 << 26), // Alternative half-precision control bit - FPSCR_DEFAULT_NAN = (1 << 25), // Default NaN mode control bit - FPSCR_FLUSH_TO_ZERO = (1 << 24), // Flush-to-zero mode control bit - FPSCR_RMODE_MASK = (3 << 22), // Rounding Mode bit mask - FPSCR_STRIDE_MASK = (3 << 20), // Vector stride bit mask - FPSCR_LENGTH_MASK = (7 << 16), // Vector length bit mask + FPSCR_QC = (1 << 27), // Cumulative saturation bit + FPSCR_AHP = (1 << 26), // Alternative half-precision control bit + FPSCR_DEFAULT_NAN = (1 << 25), // Default NaN mode control bit + FPSCR_FLUSH_TO_ZERO = (1 << 24), // Flush-to-zero mode control bit + FPSCR_RMODE_MASK = (3 << 22), // Rounding Mode bit mask + FPSCR_STRIDE_MASK = (3 << 20), // Vector stride bit mask + FPSCR_LENGTH_MASK = (7 << 16), // Vector length bit mask - FPSCR_IDE = (1 << 15), // Input Denormal exception trap enable. - FPSCR_IXE = (1 << 12), // Inexact exception trap enable - FPSCR_UFE = (1 << 11), // Undeflow exception trap enable - FPSCR_OFE = (1 << 10), // Overflow exception trap enable - FPSCR_DZE = (1 << 9), // Division by Zero exception trap enable - FPSCR_IOE = (1 << 8), // Invalid Operation exception trap enable + FPSCR_IDE = (1 << 15), // Input Denormal exception trap enable. + FPSCR_IXE = (1 << 12), // Inexact exception trap enable + FPSCR_UFE = (1 << 11), // Undeflow exception trap enable + FPSCR_OFE = (1 << 10), // Overflow exception trap enable + FPSCR_DZE = (1 << 9), // Division by Zero exception trap enable + FPSCR_IOE = (1 << 8), // Invalid Operation exception trap enable - FPSCR_IDC = (1 << 7), // Input Denormal cumulative exception bit - FPSCR_IXC = (1 << 4), // Inexact cumulative exception bit - FPSCR_UFC = (1 << 3), // Undeflow cumulative exception bit - FPSCR_OFC = (1 << 2), // Overflow cumulative exception bit - FPSCR_DZC = (1 << 1), // Division by Zero cumulative exception bit - FPSCR_IOC = (1 << 0), // Invalid Operation cumulative exception bit + FPSCR_IDC = (1 << 7), // Input Denormal cumulative exception bit + FPSCR_IXC = (1 << 4), // Inexact cumulative exception bit + FPSCR_UFC = (1 << 3), // Undeflow cumulative exception bit + FPSCR_OFC = (1 << 2), // Overflow cumulative exception bit + FPSCR_DZC = (1 << 1), // Division by Zero cumulative exception bit + FPSCR_IOC = (1 << 0), // Invalid Operation cumulative exception bit }; // FPSCR bit offsets enum : u32 { - FPSCR_RMODE_BIT = 22, + FPSCR_RMODE_BIT = 22, FPSCR_STRIDE_BIT = 20, FPSCR_LENGTH_BIT = 16, }; // FPSCR rounding modes enum : u32 { - FPSCR_ROUND_NEAREST = (0 << 22), - FPSCR_ROUND_PLUSINF = (1 << 22), + FPSCR_ROUND_NEAREST = (0 << 22), + FPSCR_ROUND_PLUSINF = (1 << 22), FPSCR_ROUND_MINUSINF = (2 << 22), - FPSCR_ROUND_TOZERO = (3 << 22) + FPSCR_ROUND_TOZERO = (3 << 22) }; diff --git a/src/core/arm/skyeye_common/vfp/vfp.cpp b/src/core/arm/skyeye_common/vfp/vfp.cpp index a27a7e194..859937645 100644 --- a/src/core/arm/skyeye_common/vfp/vfp.cpp +++ b/src/core/arm/skyeye_common/vfp/vfp.cpp @@ -28,15 +28,14 @@ #include "core/arm/skyeye_common/vfp/asm_vfp.h" #include "core/arm/skyeye_common/vfp/vfp.h" -void VFPInit(ARMul_State* state) -{ - state->VFP[VFP_FPSID] = VFP_FPSID_IMPLMEN<<24 | VFP_FPSID_SW<<23 | VFP_FPSID_SUBARCH<<16 | - VFP_FPSID_PARTNUM<<8 | VFP_FPSID_VARIANT<<4 | VFP_FPSID_REVISION; +void VFPInit(ARMul_State* state) { + state->VFP[VFP_FPSID] = VFP_FPSID_IMPLMEN << 24 | VFP_FPSID_SW << 23 | VFP_FPSID_SUBARCH << 16 | + VFP_FPSID_PARTNUM << 8 | VFP_FPSID_VARIANT << 4 | VFP_FPSID_REVISION; state->VFP[VFP_FPEXC] = 0; state->VFP[VFP_FPSCR] = 0; // ARM11 MPCore instruction register reset values. - state->VFP[VFP_FPINST] = 0xEE000A00; + state->VFP[VFP_FPINST] = 0xEE000A00; state->VFP[VFP_FPINST2] = 0; // ARM11 MPCore feature register values. @@ -44,104 +43,80 @@ void VFPInit(ARMul_State* state) state->VFP[VFP_MVFR1] = 0; } -void VMOVBRS(ARMul_State* state, u32 to_arm, u32 t, u32 n, u32* value) -{ - if (to_arm) - { +void VMOVBRS(ARMul_State* state, u32 to_arm, u32 t, u32 n, u32* value) { + if (to_arm) { *value = state->ExtReg[n]; - } - else - { + } else { state->ExtReg[n] = *value; } } -void VMOVBRRD(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2) -{ - if (to_arm) - { - *value2 = state->ExtReg[n*2+1]; - *value1 = state->ExtReg[n*2]; - } - else - { - state->ExtReg[n*2+1] = *value2; - state->ExtReg[n*2] = *value1; +void VMOVBRRD(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2) { + if (to_arm) { + *value2 = state->ExtReg[n * 2 + 1]; + *value1 = state->ExtReg[n * 2]; + } else { + state->ExtReg[n * 2 + 1] = *value2; + state->ExtReg[n * 2] = *value1; } } -void VMOVBRRSS(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2) -{ - if (to_arm) - { - *value1 = state->ExtReg[n+0]; - *value2 = state->ExtReg[n+1]; - } - else - { - state->ExtReg[n+0] = *value1; - state->ExtReg[n+1] = *value2; +void VMOVBRRSS(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2) { + if (to_arm) { + *value1 = state->ExtReg[n + 0]; + *value2 = state->ExtReg[n + 1]; + } else { + state->ExtReg[n + 0] = *value1; + state->ExtReg[n + 1] = *value2; } } -void VMOVI(ARMul_State* state, u32 single, u32 d, u32 imm) -{ - if (single) - { +void VMOVI(ARMul_State* state, u32 single, u32 d, u32 imm) { + if (single) { state->ExtReg[d] = imm; - } - else - { + } else { /* Check endian please */ - state->ExtReg[d*2+1] = imm; - state->ExtReg[d*2] = 0; + state->ExtReg[d * 2 + 1] = imm; + state->ExtReg[d * 2] = 0; } } -void VMOVR(ARMul_State* state, u32 single, u32 d, u32 m) -{ - if (single) - { +void VMOVR(ARMul_State* state, u32 single, u32 d, u32 m) { + if (single) { state->ExtReg[d] = state->ExtReg[m]; - } - else - { + } else { /* Check endian please */ - state->ExtReg[d*2+1] = state->ExtReg[m*2+1]; - state->ExtReg[d*2] = state->ExtReg[m*2]; + state->ExtReg[d * 2 + 1] = state->ExtReg[m * 2 + 1]; + state->ExtReg[d * 2] = state->ExtReg[m * 2]; } } /* Miscellaneous functions */ -s32 vfp_get_float(ARMul_State* state, unsigned int reg) -{ +s32 vfp_get_float(ARMul_State* state, unsigned int reg) { LOG_TRACE(Core_ARM11, "VFP get float: s%d=[%08x]", reg, state->ExtReg[reg]); return state->ExtReg[reg]; } -void vfp_put_float(ARMul_State* state, s32 val, unsigned int reg) -{ +void vfp_put_float(ARMul_State* state, s32 val, unsigned int reg) { LOG_TRACE(Core_ARM11, "VFP put float: s%d <= [%08x]", reg, val); state->ExtReg[reg] = val; } -u64 vfp_get_double(ARMul_State* state, unsigned int reg) -{ - u64 result = ((u64) state->ExtReg[reg*2+1])<<32 | state->ExtReg[reg*2]; +u64 vfp_get_double(ARMul_State* state, unsigned int reg) { + u64 result = ((u64)state->ExtReg[reg * 2 + 1]) << 32 | state->ExtReg[reg * 2]; LOG_TRACE(Core_ARM11, "VFP get double: s[%d-%d]=[%016llx]", reg * 2 + 1, reg * 2, result); return result; } -void vfp_put_double(ARMul_State* state, u64 val, unsigned int reg) -{ - LOG_TRACE(Core_ARM11, "VFP put double: s[%d-%d] <= [%08x-%08x]", reg * 2 + 1, reg * 2, (u32)(val >> 32), (u32)(val & 0xffffffff)); - state->ExtReg[reg*2] = (u32) (val & 0xffffffff); - state->ExtReg[reg*2+1] = (u32) (val>>32); +void vfp_put_double(ARMul_State* state, u64 val, unsigned int reg) { + LOG_TRACE(Core_ARM11, "VFP put double: s[%d-%d] <= [%08x-%08x]", reg * 2 + 1, reg * 2, + (u32)(val >> 32), (u32)(val & 0xffffffff)); + state->ExtReg[reg * 2] = (u32)(val & 0xffffffff); + state->ExtReg[reg * 2 + 1] = (u32)(val >> 32); } /* * Process bitmask of exception conditions. (from vfpmodule.c) */ -void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpscr) -{ +void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpscr) { LOG_TRACE(Core_ARM11, "VFP: raising exceptions %08x", exceptions); if (exceptions == VFP_EXCEPTION_ERROR) { @@ -154,8 +129,8 @@ void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpsc * Comparison instructions always return at least one of * these flags set. */ - if (exceptions & (FPSCR_NFLAG|FPSCR_ZFLAG|FPSCR_CFLAG|FPSCR_VFLAG)) - fpscr &= ~(FPSCR_NFLAG|FPSCR_ZFLAG|FPSCR_CFLAG|FPSCR_VFLAG); + if (exceptions & (FPSCR_NFLAG | FPSCR_ZFLAG | FPSCR_CFLAG | FPSCR_VFLAG)) + fpscr &= ~(FPSCR_NFLAG | FPSCR_ZFLAG | FPSCR_CFLAG | FPSCR_VFLAG); fpscr |= exceptions; diff --git a/src/core/arm/skyeye_common/vfp/vfp_helper.h b/src/core/arm/skyeye_common/vfp/vfp_helper.h index 68714800c..5e14345ce 100644 --- a/src/core/arm/skyeye_common/vfp/vfp_helper.h +++ b/src/core/arm/skyeye_common/vfp/vfp_helper.h @@ -37,56 +37,56 @@ #include "core/arm/skyeye_common/armstate.h" #include "core/arm/skyeye_common/vfp/asm_vfp.h" -#define do_div(n, base) {n/=base;} +#define do_div(n, base) \ + { n /= base; } enum : u32 { - FOP_MASK = 0x00b00040, - FOP_FMAC = 0x00000000, + FOP_MASK = 0x00b00040, + FOP_FMAC = 0x00000000, FOP_FNMAC = 0x00000040, - FOP_FMSC = 0x00100000, + FOP_FMSC = 0x00100000, FOP_FNMSC = 0x00100040, - FOP_FMUL = 0x00200000, + FOP_FMUL = 0x00200000, FOP_FNMUL = 0x00200040, - FOP_FADD = 0x00300000, - FOP_FSUB = 0x00300040, - FOP_FDIV = 0x00800000, - FOP_EXT = 0x00b00040 + FOP_FADD = 0x00300000, + FOP_FSUB = 0x00300040, + FOP_FDIV = 0x00800000, + FOP_EXT = 0x00b00040 }; #define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4) enum : u32 { - FEXT_MASK = 0x000f0080, - FEXT_FCPY = 0x00000000, - FEXT_FABS = 0x00000080, - FEXT_FNEG = 0x00010000, - FEXT_FSQRT = 0x00010080, - FEXT_FCMP = 0x00040000, - FEXT_FCMPE = 0x00040080, - FEXT_FCMPZ = 0x00050000, + FEXT_MASK = 0x000f0080, + FEXT_FCPY = 0x00000000, + FEXT_FABS = 0x00000080, + FEXT_FNEG = 0x00010000, + FEXT_FSQRT = 0x00010080, + FEXT_FCMP = 0x00040000, + FEXT_FCMPE = 0x00040080, + FEXT_FCMPZ = 0x00050000, FEXT_FCMPEZ = 0x00050080, - FEXT_FCVT = 0x00070080, - FEXT_FUITO = 0x00080000, - FEXT_FSITO = 0x00080080, - FEXT_FTOUI = 0x000c0000, + FEXT_FCVT = 0x00070080, + FEXT_FUITO = 0x00080000, + FEXT_FSITO = 0x00080080, + FEXT_FTOUI = 0x000c0000, FEXT_FTOUIZ = 0x000c0080, - FEXT_FTOSI = 0x000d0000, + FEXT_FTOSI = 0x000d0000, FEXT_FTOSIZ = 0x000d0080 }; #define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7) -#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22) -#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18) -#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5) -#define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1) -#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7) -#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3) +#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22) +#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18) +#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5) +#define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1) +#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7) +#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3) -#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00) +#define vfp_single(inst) (((inst)&0x0000f00) == 0xa00) -inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift) -{ +inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift) { if (shift) { if (shift < 32) val = val >> shift | ((val << (32 - shift)) != 0); @@ -96,8 +96,7 @@ inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift) return val; } -inline u64 vfp_shiftright64jamming(u64 val, unsigned int shift) -{ +inline u64 vfp_shiftright64jamming(u64 val, unsigned int shift) { if (shift) { if (shift < 64) val = val >> shift | ((val << (64 - shift)) != 0); @@ -107,8 +106,7 @@ inline u64 vfp_shiftright64jamming(u64 val, unsigned int shift) return val; } -inline u32 vfp_hi64to32jamming(u64 val) -{ +inline u32 vfp_hi64to32jamming(u64 val) { u32 v; u32 highval = val >> 32; u32 lowval = val & 0xffffffff; @@ -121,24 +119,21 @@ inline u32 vfp_hi64to32jamming(u64 val) return v; } -inline void add128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml) -{ +inline void add128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml) { *resl = nl + ml; *resh = nh + mh; if (*resl < nl) *resh += 1; } -inline void sub128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml) -{ +inline void sub128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml) { *resl = nl - ml; *resh = nh - mh; if (*resl > nl) *resh -= 1; } -inline void mul64to128(u64* resh, u64* resl, u64 n, u64 m) -{ +inline void mul64to128(u64* resh, u64* resl, u64 n, u64 m) { u32 nh, nl, mh, ml; u64 rh, rma, rmb, rl; @@ -164,21 +159,18 @@ inline void mul64to128(u64* resh, u64* resl, u64 n, u64 m) *resh = rh; } -inline void shift64left(u64* resh, u64* resl, u64 n) -{ +inline void shift64left(u64* resh, u64* resl, u64 n) { *resh = n >> 63; *resl = n << 1; } -inline u64 vfp_hi64multiply64(u64 n, u64 m) -{ +inline u64 vfp_hi64multiply64(u64 n, u64 m) { u64 rh, rl; mul64to128(&rh, &rl, n, m); return rh | (rl != 0); } -inline u64 vfp_estimate_div128to64(u64 nh, u64 nl, u64 m) -{ +inline u64 vfp_estimate_div128to64(u64 nh, u64 nl, u64 m) { u64 mh, ml, remh, reml, termh, terml, z; if (nh >= m) @@ -213,9 +205,9 @@ inline u64 vfp_estimate_div128to64(u64 nh, u64 nl, u64 m) // Single-precision struct vfp_single { - s16 exponent; - u16 sign; - u32 significand; + s16 exponent; + u16 sign; + u32 significand; }; // VFP_SINGLE_MANTISSA_BITS - number of bits in the mantissa @@ -224,33 +216,33 @@ struct vfp_single { // which are not propagated to the float upon packing. #define VFP_SINGLE_MANTISSA_BITS (23) #define VFP_SINGLE_EXPONENT_BITS (8) -#define VFP_SINGLE_LOW_BITS (32 - VFP_SINGLE_MANTISSA_BITS - 2) +#define VFP_SINGLE_LOW_BITS (32 - VFP_SINGLE_MANTISSA_BITS - 2) #define VFP_SINGLE_LOW_BITS_MASK ((1 << VFP_SINGLE_LOW_BITS) - 1) // The bit in an unpacked float which indicates that it is a quiet NaN -#define VFP_SINGLE_SIGNIFICAND_QNAN (1 << (VFP_SINGLE_MANTISSA_BITS - 1 + VFP_SINGLE_LOW_BITS)) +#define VFP_SINGLE_SIGNIFICAND_QNAN (1 << (VFP_SINGLE_MANTISSA_BITS - 1 + VFP_SINGLE_LOW_BITS)) // Operations on packed single-precision numbers -#define vfp_single_packed_sign(v) ((v) & 0x80000000) -#define vfp_single_packed_negate(v) ((v) ^ 0x80000000) -#define vfp_single_packed_abs(v) ((v) & ~0x80000000) -#define vfp_single_packed_exponent(v) (((v) >> VFP_SINGLE_MANTISSA_BITS) & ((1 << VFP_SINGLE_EXPONENT_BITS) - 1)) +#define vfp_single_packed_sign(v) ((v)&0x80000000) +#define vfp_single_packed_negate(v) ((v) ^ 0x80000000) +#define vfp_single_packed_abs(v) ((v) & ~0x80000000) +#define vfp_single_packed_exponent(v) \ + (((v) >> VFP_SINGLE_MANTISSA_BITS) & ((1 << VFP_SINGLE_EXPONENT_BITS) - 1)) #define vfp_single_packed_mantissa(v) ((v) & ((1 << VFP_SINGLE_MANTISSA_BITS) - 1)) enum : u32 { - VFP_NUMBER = (1 << 0), - VFP_ZERO = (1 << 1), - VFP_DENORMAL = (1 << 2), - VFP_INFINITY = (1 << 3), - VFP_NAN = (1 << 4), + VFP_NUMBER = (1 << 0), + VFP_ZERO = (1 << 1), + VFP_DENORMAL = (1 << 2), + VFP_INFINITY = (1 << 3), + VFP_NAN = (1 << 4), VFP_NAN_SIGNAL = (1 << 5), - VFP_QNAN = (VFP_NAN), - VFP_SNAN = (VFP_NAN|VFP_NAN_SIGNAL) + VFP_QNAN = (VFP_NAN), + VFP_SNAN = (VFP_NAN | VFP_NAN_SIGNAL) }; -inline int vfp_single_type(const vfp_single* s) -{ +inline int vfp_single_type(const vfp_single* s) { int type = VFP_NUMBER; if (s->exponent == 255) { if (s->significand == 0) @@ -271,11 +263,9 @@ inline int vfp_single_type(const vfp_single* s) // Unpack a single-precision float. Note that this returns the magnitude // of the single-precision float mantissa with the 1. if necessary, // aligned to bit 30. -inline u32 vfp_single_unpack(vfp_single* s, s32 val, u32 fpscr) -{ +inline u32 vfp_single_unpack(vfp_single* s, s32 val, u32 fpscr) { u32 exceptions = 0; - s->sign = vfp_single_packed_sign(val) >> 16, - s->exponent = vfp_single_packed_exponent(val); + s->sign = vfp_single_packed_sign(val) >> 16, s->exponent = vfp_single_packed_exponent(val); u32 significand = ((u32)val << (32 - VFP_SINGLE_MANTISSA_BITS)) >> 2; if (s->exponent && s->exponent != 255) @@ -295,22 +285,20 @@ inline u32 vfp_single_unpack(vfp_single* s, s32 val, u32 fpscr) // Re-pack a single-precision float. This assumes that the float is // already normalised such that the MSB is bit 30, _not_ bit 31. -inline s32 vfp_single_pack(const vfp_single* s) -{ - u32 val = (s->sign << 16) + - (s->exponent << VFP_SINGLE_MANTISSA_BITS) + +inline s32 vfp_single_pack(const vfp_single* s) { + u32 val = (s->sign << 16) + (s->exponent << VFP_SINGLE_MANTISSA_BITS) + (s->significand >> VFP_SINGLE_LOW_BITS); return (s32)val; } - -u32 vfp_single_normaliseround(ARMul_State* state, int sd, vfp_single* vs, u32 fpscr, const char* func); +u32 vfp_single_normaliseround(ARMul_State* state, int sd, vfp_single* vs, u32 fpscr, + const char* func); // Double-precision struct vfp_double { - s16 exponent; - u16 sign; - u64 significand; + s16 exponent; + u16 sign; + u64 significand; }; // VFP_REG_ZERO is a special register number for vfp_get_double @@ -324,21 +312,21 @@ struct vfp_double { #define VFP_DOUBLE_MANTISSA_BITS (52) #define VFP_DOUBLE_EXPONENT_BITS (11) -#define VFP_DOUBLE_LOW_BITS (64 - VFP_DOUBLE_MANTISSA_BITS - 2) +#define VFP_DOUBLE_LOW_BITS (64 - VFP_DOUBLE_MANTISSA_BITS - 2) #define VFP_DOUBLE_LOW_BITS_MASK ((1 << VFP_DOUBLE_LOW_BITS) - 1) // The bit in an unpacked double which indicates that it is a quiet NaN #define VFP_DOUBLE_SIGNIFICAND_QNAN (1ULL << (VFP_DOUBLE_MANTISSA_BITS - 1 + VFP_DOUBLE_LOW_BITS)) // Operations on packed single-precision numbers -#define vfp_double_packed_sign(v) ((v) & (1ULL << 63)) -#define vfp_double_packed_negate(v) ((v) ^ (1ULL << 63)) -#define vfp_double_packed_abs(v) ((v) & ~(1ULL << 63)) -#define vfp_double_packed_exponent(v) (((v) >> VFP_DOUBLE_MANTISSA_BITS) & ((1 << VFP_DOUBLE_EXPONENT_BITS) - 1)) +#define vfp_double_packed_sign(v) ((v) & (1ULL << 63)) +#define vfp_double_packed_negate(v) ((v) ^ (1ULL << 63)) +#define vfp_double_packed_abs(v) ((v) & ~(1ULL << 63)) +#define vfp_double_packed_exponent(v) \ + (((v) >> VFP_DOUBLE_MANTISSA_BITS) & ((1 << VFP_DOUBLE_EXPONENT_BITS) - 1)) #define vfp_double_packed_mantissa(v) ((v) & ((1ULL << VFP_DOUBLE_MANTISSA_BITS) - 1)) -inline int vfp_double_type(const vfp_double* s) -{ +inline int vfp_double_type(const vfp_double* s) { int type = VFP_NUMBER; if (s->exponent == 2047) { if (s->significand == 0) @@ -359,8 +347,7 @@ inline int vfp_double_type(const vfp_double* s) // Unpack a double-precision float. Note that this returns the magnitude // of the double-precision float mantissa with the 1. if necessary, // aligned to bit 62. -inline u32 vfp_double_unpack(vfp_double* s, s64 val, u32 fpscr) -{ +inline u32 vfp_double_unpack(vfp_double* s, s64 val, u32 fpscr) { u32 exceptions = 0; s->sign = vfp_double_packed_sign(val) >> 48; s->exponent = vfp_double_packed_exponent(val); @@ -383,10 +370,8 @@ inline u32 vfp_double_unpack(vfp_double* s, s64 val, u32 fpscr) // Re-pack a double-precision float. This assumes that the float is // already normalised such that the MSB is bit 30, _not_ bit 31. -inline s64 vfp_double_pack(const vfp_double* s) -{ - u64 val = ((u64)s->sign << 48) + - ((u64)s->exponent << VFP_DOUBLE_MANTISSA_BITS) + +inline s64 vfp_double_pack(const vfp_double* s) { + u64 val = ((u64)s->sign << 48) + ((u64)s->exponent << VFP_DOUBLE_MANTISSA_BITS) + (s->significand >> VFP_DOUBLE_LOW_BITS); return (s64)val; } @@ -407,20 +392,14 @@ u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand); // OP_SD - The instruction exceptionally writes to a single precision result. // OP_DD - The instruction exceptionally writes to a double precision result. // OP_SM - The instruction exceptionally reads from a single precision operand. -enum : u32 { - OP_SCALAR = (1 << 0), - OP_SD = (1 << 1), - OP_DD = (1 << 1), - OP_SM = (1 << 2) -}; +enum : u32 { OP_SCALAR = (1 << 0), OP_SD = (1 << 1), OP_DD = (1 << 1), OP_SM = (1 << 2) }; struct op { - u32 (* const fn)(ARMul_State* state, int dd, int dn, int dm, u32 fpscr); + u32 (*const fn)(ARMul_State* state, int dd, int dn, int dm, u32 fpscr); u32 flags; }; -inline u32 fls(u32 x) -{ +inline u32 fls(u32 x) { int r = 32; if (!x) @@ -446,9 +425,9 @@ inline u32 fls(u32 x) r -= 1; } return r; - } u32 vfp_double_multiply(vfp_double* vdd, vfp_double* vdn, vfp_double* vdm, u32 fpscr); -u32 vfp_double_add(vfp_double* vdd, vfp_double* vdn, vfp_double *vdm, u32 fpscr); -u32 vfp_double_normaliseround(ARMul_State* state, int dd, vfp_double* vd, u32 fpscr, const char* func); +u32 vfp_double_add(vfp_double* vdd, vfp_double* vdn, vfp_double* vdm, u32 fpscr); +u32 vfp_double_normaliseround(ARMul_State* state, int dd, vfp_double* vd, u32 fpscr, + const char* func); diff --git a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp index 1d5641810..4d89743e7 100644 --- a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp +++ b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp @@ -51,26 +51,22 @@ * =========================================================================== */ +#include "core/arm/skyeye_common/vfp/vfp.h" #include <algorithm> #include "common/logging/log.h" -#include "core/arm/skyeye_common/vfp/vfp.h" -#include "core/arm/skyeye_common/vfp/vfp_helper.h" #include "core/arm/skyeye_common/vfp/asm_vfp.h" +#include "core/arm/skyeye_common/vfp/vfp_helper.h" static struct vfp_double vfp_double_default_qnan = { - 2047, - 0, - VFP_DOUBLE_SIGNIFICAND_QNAN, + 2047, 0, VFP_DOUBLE_SIGNIFICAND_QNAN, }; -static void vfp_double_dump(const char *str, struct vfp_double *d) -{ - LOG_TRACE(Core_ARM11, "VFP: %s: sign=%d exponent=%d significand=%016llx", - str, d->sign != 0, d->exponent, d->significand); +static void vfp_double_dump(const char* str, struct vfp_double* d) { + LOG_TRACE(Core_ARM11, "VFP: %s: sign=%d exponent=%d significand=%016llx", str, d->sign != 0, + d->exponent, d->significand); } -static void vfp_double_normalise_denormal(struct vfp_double *vd) -{ +static void vfp_double_normalise_denormal(struct vfp_double* vd) { int bits = 31 - fls((u32)(vd->significand >> 32)); if (bits == 31) bits = 63 - fls((u32)vd->significand); @@ -85,8 +81,8 @@ static void vfp_double_normalise_denormal(struct vfp_double *vd) vfp_double_dump("normalise_denormal: out", vd); } -u32 vfp_double_normaliseround(ARMul_State* state, int dd, struct vfp_double *vd, u32 fpscr, const char *func) -{ +u32 vfp_double_normaliseround(ARMul_State* state, int dd, struct vfp_double* vd, u32 fpscr, + const char* func) { u64 significand, incr; int exponent, shift, underflow; u32 rmode; @@ -193,7 +189,7 @@ u32 vfp_double_normaliseround(ARMul_State* state, int dd, struct vfp_double *vd, vd->exponent = 2045; vd->significand = 0x7fffffffffffffffULL; } else { - vd->exponent = 2047; /* infinity */ + vd->exponent = 2047; /* infinity */ vd->significand = 0; } } else { @@ -211,8 +207,7 @@ pack: vfp_double_dump("pack: final", vd); { s64 d = vfp_double_pack(vd); - LOG_TRACE(Core_ARM11, "VFP: %s: d(d%d)=%016llx exceptions=%08x", func, - dd, d, exceptions); + LOG_TRACE(Core_ARM11, "VFP: %s: d(d%d)=%016llx exceptions=%08x", func, dd, d, exceptions); vfp_put_double(state, d, dd); } return exceptions; @@ -222,11 +217,9 @@ pack: * Propagate the NaN, setting exceptions if it is signalling. * 'n' is always a NaN. 'm' may be a number, NaN or infinity. */ -static u32 -vfp_propagate_nan(struct vfp_double *vdd, struct vfp_double *vdn, - struct vfp_double *vdm, u32 fpscr) -{ - struct vfp_double *nan; +static u32 vfp_propagate_nan(struct vfp_double* vdd, struct vfp_double* vdn, struct vfp_double* vdm, + u32 fpscr) { + struct vfp_double* nan; int tn, tm = 0; tn = vfp_double_type(vdn); @@ -266,29 +259,25 @@ vfp_propagate_nan(struct vfp_double *vdd, struct vfp_double *vdn, /* * Extended operations */ -static u32 vfp_double_fabs(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) -{ +static u32 vfp_double_fabs(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); vfp_put_double(state, vfp_double_packed_abs(vfp_get_double(state, dm)), dd); return 0; } -static u32 vfp_double_fcpy(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) -{ +static u32 vfp_double_fcpy(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); vfp_put_double(state, vfp_get_double(state, dm), dd); return 0; } -static u32 vfp_double_fneg(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) -{ +static u32 vfp_double_fneg(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); vfp_put_double(state, vfp_double_packed_negate(vfp_get_double(state, dm)), dd); return 0; } -static u32 vfp_double_fsqrt(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) -{ +static u32 vfp_double_fsqrt(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); vfp_double vdm, vdd, *vdp; int ret, tm; @@ -297,17 +286,17 @@ static u32 vfp_double_fsqrt(ARMul_State* state, int dd, int unused, int dm, u32 exceptions |= vfp_double_unpack(&vdm, vfp_get_double(state, dm), fpscr); tm = vfp_double_type(&vdm); - if (tm & (VFP_NAN|VFP_INFINITY)) { + if (tm & (VFP_NAN | VFP_INFINITY)) { vdp = &vdd; if (tm & VFP_NAN) ret = vfp_propagate_nan(vdp, &vdm, nullptr, fpscr); else if (vdm.sign == 0) { -sqrt_copy: + sqrt_copy: vdp = &vdm; ret = 0; } else { -sqrt_invalid: + sqrt_invalid: vdp = &vfp_double_default_qnan; ret = FPSCR_IOC; } @@ -381,8 +370,7 @@ sqrt_invalid: * Greater than := C * Unordered := CV */ -static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u32 fpscr) -{ +static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u32 fpscr) { s64 d, m; u32 ret = 0; @@ -390,7 +378,8 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u m = vfp_get_double(state, dm); if (vfp_double_packed_exponent(m) == 2047 && vfp_double_packed_mantissa(m)) { ret |= FPSCR_CFLAG | FPSCR_VFLAG; - if (signal_on_qnan || !(vfp_double_packed_mantissa(m) & (1ULL << (VFP_DOUBLE_MANTISSA_BITS - 1)))) + if (signal_on_qnan || + !(vfp_double_packed_mantissa(m) & (1ULL << (VFP_DOUBLE_MANTISSA_BITS - 1)))) /* * Signalling NaN, or signalling on quiet NaN */ @@ -400,7 +389,8 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u d = vfp_get_double(state, dd); if (vfp_double_packed_exponent(d) == 2047 && vfp_double_packed_mantissa(d)) { ret |= FPSCR_CFLAG | FPSCR_VFLAG; - if (signal_on_qnan || !(vfp_double_packed_mantissa(d) & (1ULL << (VFP_DOUBLE_MANTISSA_BITS - 1)))) + if (signal_on_qnan || + !(vfp_double_packed_mantissa(d) & (1ULL << (VFP_DOUBLE_MANTISSA_BITS - 1)))) /* * Signalling NaN, or signalling on quiet NaN */ @@ -408,13 +398,13 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u } if (ret == 0) { - //printf("In %s, d=%lld, m =%lld\n ", __FUNCTION__, d, m); + // printf("In %s, d=%lld, m =%lld\n ", __FUNCTION__, d, m); if (d == m || vfp_double_packed_abs(d | m) == 0) { /* * equal */ ret |= FPSCR_ZFLAG | FPSCR_CFLAG; - //printf("In %s,1 ret=0x%x\n", __FUNCTION__, ret); + // printf("In %s,1 ret=0x%x\n", __FUNCTION__, ret); } else if (vfp_double_packed_sign(d ^ m)) { /* * different signs @@ -446,32 +436,27 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u return ret; } -static u32 vfp_double_fcmp(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) -{ +static u32 vfp_double_fcmp(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); return vfp_compare(state, dd, 0, dm, fpscr); } -static u32 vfp_double_fcmpe(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) -{ +static u32 vfp_double_fcmpe(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); return vfp_compare(state, dd, 1, dm, fpscr); } -static u32 vfp_double_fcmpz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) -{ +static u32 vfp_double_fcmpz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); return vfp_compare(state, dd, 0, VFP_REG_ZERO, fpscr); } -static u32 vfp_double_fcmpez(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) -{ +static u32 vfp_double_fcmpez(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); return vfp_compare(state, dd, 1, VFP_REG_ZERO, fpscr); } -static u32 vfp_double_fcvts(ARMul_State* state, int sd, int unused, int dm, u32 fpscr) -{ +static u32 vfp_double_fcvts(ARMul_State* state, int sd, int unused, int dm, u32 fpscr) { struct vfp_double vdm; struct vfp_single vsd; int tm; @@ -497,7 +482,7 @@ static u32 vfp_double_fcvts(ARMul_State* state, int sd, int unused, int dm, u32 /* * If we have an infinity or a NaN, the exponent must be 255 */ - if (tm & (VFP_INFINITY|VFP_NAN)) { + if (tm & (VFP_INFINITY | VFP_NAN)) { vsd.exponent = 255; if (tm == VFP_QNAN) vsd.significand |= VFP_SINGLE_SIGNIFICAND_QNAN; @@ -515,8 +500,7 @@ pack_nan: return exceptions; } -static u32 vfp_double_fuito(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) -{ +static u32 vfp_double_fuito(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { struct vfp_double vdm; u32 exceptions = 0; u32 m = vfp_get_float(state, dm); @@ -530,8 +514,7 @@ static u32 vfp_double_fuito(ARMul_State* state, int dd, int unused, int dm, u32 return exceptions; } -static u32 vfp_double_fsito(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) -{ +static u32 vfp_double_fsito(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { struct vfp_double vdm; u32 exceptions = 0; u32 m = vfp_get_float(state, dm); @@ -545,8 +528,7 @@ static u32 vfp_double_fsito(ARMul_State* state, int dd, int unused, int dm, u32 return exceptions; } -static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32 fpscr) -{ +static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32 fpscr) { struct vfp_double vdm; u32 d, exceptions = 0; int rmode = fpscr & FPSCR_RMODE_MASK; @@ -628,14 +610,13 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32 return exceptions; } -static u32 vfp_double_ftouiz(ARMul_State* state, int sd, int unused, int dm, u32 fpscr) -{ +static u32 vfp_double_ftouiz(ARMul_State* state, int sd, int unused, int dm, u32 fpscr) { LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); - return vfp_double_ftoui(state, sd, unused, dm, (fpscr & ~FPSCR_RMODE_MASK) | FPSCR_ROUND_TOZERO); + return vfp_double_ftoui(state, sd, unused, dm, + (fpscr & ~FPSCR_RMODE_MASK) | FPSCR_ROUND_TOZERO); } -static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32 fpscr) -{ +static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32 fpscr) { struct vfp_double vdm; u32 d, exceptions = 0; int rmode = fpscr & FPSCR_RMODE_MASK; @@ -661,7 +642,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32 d = ~d; exceptions |= FPSCR_IOC; } else if (vdm.exponent >= 1023) { - int shift = 1023 + 63 - vdm.exponent; /* 58 */ + int shift = 1023 + 63 - vdm.exponent; /* 58 */ u64 rem, incr = 0; d = (u32)((vdm.significand << 1) >> shift); @@ -712,48 +693,46 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32 return exceptions; } -static u32 vfp_double_ftosiz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) -{ +static u32 vfp_double_ftosiz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) { LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); - return vfp_double_ftosi(state, dd, unused, dm, (fpscr & ~FPSCR_RMODE_MASK) | FPSCR_ROUND_TOZERO); + return vfp_double_ftosi(state, dd, unused, dm, + (fpscr & ~FPSCR_RMODE_MASK) | FPSCR_ROUND_TOZERO); } static struct op fops_ext[] = { - { vfp_double_fcpy, 0 }, //0x00000000 - FEXT_FCPY - { vfp_double_fabs, 0 }, //0x00000001 - FEXT_FABS - { vfp_double_fneg, 0 }, //0x00000002 - FEXT_FNEG - { vfp_double_fsqrt, 0 }, //0x00000003 - FEXT_FSQRT - { nullptr, 0 }, - { nullptr, 0 }, - { nullptr, 0 }, - { nullptr, 0 }, - { vfp_double_fcmp, OP_SCALAR }, //0x00000008 - FEXT_FCMP - { vfp_double_fcmpe, OP_SCALAR }, //0x00000009 - FEXT_FCMPE - { vfp_double_fcmpz, OP_SCALAR }, //0x0000000A - FEXT_FCMPZ - { vfp_double_fcmpez, OP_SCALAR }, //0x0000000B - FEXT_FCMPEZ - { nullptr, 0 }, - { nullptr, 0 }, - { nullptr, 0 }, - { vfp_double_fcvts, OP_SCALAR|OP_DD }, //0x0000000F - FEXT_FCVT - { vfp_double_fuito, OP_SCALAR|OP_SM }, //0x00000010 - FEXT_FUITO - { vfp_double_fsito, OP_SCALAR|OP_SM }, //0x00000011 - FEXT_FSITO - { nullptr, 0 }, - { nullptr, 0 }, - { nullptr, 0 }, - { nullptr, 0 }, - { nullptr, 0 }, - { nullptr, 0 }, - { vfp_double_ftoui, OP_SCALAR|OP_SD }, //0x00000018 - FEXT_FTOUI - { vfp_double_ftouiz, OP_SCALAR|OP_SD }, //0x00000019 - FEXT_FTOUIZ - { vfp_double_ftosi, OP_SCALAR|OP_SD }, //0x0000001A - FEXT_FTOSI - { vfp_double_ftosiz, OP_SCALAR|OP_SD }, //0x0000001B - FEXT_FTOSIZ + {vfp_double_fcpy, 0}, // 0x00000000 - FEXT_FCPY + {vfp_double_fabs, 0}, // 0x00000001 - FEXT_FABS + {vfp_double_fneg, 0}, // 0x00000002 - FEXT_FNEG + {vfp_double_fsqrt, 0}, // 0x00000003 - FEXT_FSQRT + {nullptr, 0}, + {nullptr, 0}, + {nullptr, 0}, + {nullptr, 0}, + {vfp_double_fcmp, OP_SCALAR}, // 0x00000008 - FEXT_FCMP + {vfp_double_fcmpe, OP_SCALAR}, // 0x00000009 - FEXT_FCMPE + {vfp_double_fcmpz, OP_SCALAR}, // 0x0000000A - FEXT_FCMPZ + {vfp_double_fcmpez, OP_SCALAR}, // 0x0000000B - FEXT_FCMPEZ + {nullptr, 0}, + {nullptr, 0}, + {nullptr, 0}, + {vfp_double_fcvts, OP_SCALAR | OP_DD}, // 0x0000000F - FEXT_FCVT + {vfp_double_fuito, OP_SCALAR | OP_SM}, // 0x00000010 - FEXT_FUITO + {vfp_double_fsito, OP_SCALAR | OP_SM}, // 0x00000011 - FEXT_FSITO + {nullptr, 0}, + {nullptr, 0}, + {nullptr, 0}, + {nullptr, 0}, + {nullptr, 0}, + {nullptr, 0}, + {vfp_double_ftoui, OP_SCALAR | OP_SD}, // 0x00000018 - FEXT_FTOUI + {vfp_double_ftouiz, OP_SCALAR | OP_SD}, // 0x00000019 - FEXT_FTOUIZ + {vfp_double_ftosi, OP_SCALAR | OP_SD}, // 0x0000001A - FEXT_FTOSI + {vfp_double_ftosiz, OP_SCALAR | OP_SD}, // 0x0000001B - FEXT_FTOSIZ }; -static u32 -vfp_double_fadd_nonnumber(struct vfp_double *vdd, struct vfp_double *vdn, - struct vfp_double *vdm, u32 fpscr) -{ - struct vfp_double *vdp; +static u32 vfp_double_fadd_nonnumber(struct vfp_double* vdd, struct vfp_double* vdn, + struct vfp_double* vdm, u32 fpscr) { + struct vfp_double* vdp; u32 exceptions = 0; int tn, tm; @@ -791,13 +770,12 @@ vfp_double_fadd_nonnumber(struct vfp_double *vdd, struct vfp_double *vdn, return exceptions; } -u32 vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn,struct vfp_double *vdm, u32 fpscr) -{ +u32 vfp_double_add(struct vfp_double* vdd, struct vfp_double* vdn, struct vfp_double* vdm, + u32 fpscr) { u32 exp_diff; u64 m_sig; - if (vdn->significand & (1ULL << 63) || - vdm->significand & (1ULL << 63)) { + if (vdn->significand & (1ULL << 63) || vdm->significand & (1ULL << 63)) { LOG_INFO(Core_ARM11, "VFP: bad FP values in %s", __func__); vfp_double_dump("VDN", vdn); vfp_double_dump("VDM", vdm); @@ -841,8 +819,7 @@ u32 vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn,struct vfp_dou vdd->sign = vfp_sign_negate(vdd->sign); m_sig = (~m_sig + 1); } else if (m_sig == 0) { - vdd->sign = (fpscr & FPSCR_RMODE_MASK) == - FPSCR_ROUND_MINUSINF ? 0x8000 : 0; + vdd->sign = (fpscr & FPSCR_RMODE_MASK) == FPSCR_ROUND_MINUSINF ? 0x8000 : 0; } } else { m_sig += vdn->significand; @@ -852,10 +829,8 @@ u32 vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn,struct vfp_dou return 0; } -u32 -vfp_double_multiply(struct vfp_double *vdd, struct vfp_double *vdn, - struct vfp_double *vdm, u32 fpscr) -{ +u32 vfp_double_multiply(struct vfp_double* vdd, struct vfp_double* vdn, struct vfp_double* vdm, + u32 fpscr) { vfp_double_dump("VDN", vdn); vfp_double_dump("VDM", vdm); @@ -908,12 +883,11 @@ vfp_double_multiply(struct vfp_double *vdd, struct vfp_double *vdn, return 0; } -#define NEG_MULTIPLY (1 << 0) -#define NEG_SUBTRACT (1 << 1) +#define NEG_MULTIPLY (1 << 0) +#define NEG_SUBTRACT (1 << 1) -static u32 -vfp_double_multiply_accumulate(ARMul_State* state, int dd, int dn, int dm, u32 fpscr, u32 negate, const char *func) -{ +static u32 vfp_double_multiply_accumulate(ARMul_State* state, int dd, int dn, int dm, u32 fpscr, + u32 negate, const char* func) { struct vfp_double vdd, vdp, vdn, vdm; u32 exceptions = 0; @@ -949,8 +923,7 @@ vfp_double_multiply_accumulate(ARMul_State* state, int dd, int dn, int dm, u32 f /* * sd = sd + (sn * sm) */ -static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) -{ +static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) { LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, 0, "fmac"); } @@ -958,8 +931,7 @@ static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr /* * sd = sd - (sn * sm) */ -static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) -{ +static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) { LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_MULTIPLY, "fnmac"); } @@ -967,8 +939,7 @@ static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpsc /* * sd = -sd + (sn * sm) */ -static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) -{ +static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) { LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT, "fmsc"); } @@ -976,17 +947,16 @@ static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr /* * sd = -sd - (sn * sm) */ -static u32 vfp_double_fnmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) -{ +static u32 vfp_double_fnmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) { LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); - return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT | NEG_MULTIPLY, "fnmsc"); + return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT | NEG_MULTIPLY, + "fnmsc"); } /* * sd = sn * sm */ -static u32 vfp_double_fmul(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) -{ +static u32 vfp_double_fmul(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) { struct vfp_double vdd, vdn, vdm; u32 exceptions = 0; @@ -1008,8 +978,7 @@ static u32 vfp_double_fmul(ARMul_State* state, int dd, int dn, int dm, u32 fpscr /* * sd = -(sn * sm) */ -static u32 vfp_double_fnmul(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) -{ +static u32 vfp_double_fnmul(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) { struct vfp_double vdd, vdn, vdm; u32 exceptions = 0; @@ -1032,8 +1001,7 @@ static u32 vfp_double_fnmul(ARMul_State* state, int dd, int dn, int dm, u32 fpsc /* * sd = sn + sm */ -static u32 vfp_double_fadd(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) -{ +static u32 vfp_double_fadd(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) { struct vfp_double vdd, vdn, vdm; u32 exceptions = 0; @@ -1055,8 +1023,7 @@ static u32 vfp_double_fadd(ARMul_State* state, int dd, int dn, int dm, u32 fpscr /* * sd = sn - sm */ -static u32 vfp_double_fsub(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) -{ +static u32 vfp_double_fsub(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) { struct vfp_double vdd, vdn, vdm; u32 exceptions = 0; @@ -1083,8 +1050,7 @@ static u32 vfp_double_fsub(ARMul_State* state, int dd, int dn, int dm, u32 fpscr /* * sd = sn / sm */ -static u32 vfp_double_fdiv(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) -{ +static u32 vfp_double_fdiv(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) { struct vfp_double vdd, vdn, vdm; u32 exceptions = 0; int tm, tn; @@ -1114,7 +1080,7 @@ static u32 vfp_double_fdiv(ARMul_State* state, int dd, int dn, int dm, u32 fpscr * If n and m are infinity, the result is invalid * If n and m are zero, the result is invalid */ - if (tm & tn & (VFP_INFINITY|VFP_ZERO)) + if (tm & tn & (VFP_INFINITY | VFP_ZERO)) goto invalid; /* @@ -1193,29 +1159,22 @@ invalid: } static struct op fops[] = { - { vfp_double_fmac, 0 }, - { vfp_double_fmsc, 0 }, - { vfp_double_fmul, 0 }, - { vfp_double_fadd, 0 }, - { vfp_double_fnmac, 0 }, - { vfp_double_fnmsc, 0 }, - { vfp_double_fnmul, 0 }, - { vfp_double_fsub, 0 }, - { vfp_double_fdiv, 0 }, + {vfp_double_fmac, 0}, {vfp_double_fmsc, 0}, {vfp_double_fmul, 0}, + {vfp_double_fadd, 0}, {vfp_double_fnmac, 0}, {vfp_double_fnmsc, 0}, + {vfp_double_fnmul, 0}, {vfp_double_fsub, 0}, {vfp_double_fdiv, 0}, }; -#define FREG_BANK(x) ((x) & 0x0c) -#define FREG_IDX(x) ((x) & 3) +#define FREG_BANK(x) ((x)&0x0c) +#define FREG_IDX(x) ((x)&3) -u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr) -{ +u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr) { u32 op = inst & FOP_MASK; u32 exceptions = 0; unsigned int dest; unsigned int dn = vfp_get_dn(inst); unsigned int dm; unsigned int vecitr, veclen, vecstride; - struct op *fop; + struct op* fop; LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__); vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)); @@ -1249,7 +1208,7 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr) veclen = fpscr & FPSCR_LENGTH_MASK; LOG_TRACE(Core_ARM11, "VFP: vecstride=%u veclen=%u", vecstride, - (veclen >> FPSCR_LENGTH_BIT) + 1); + (veclen >> FPSCR_LENGTH_BIT) + 1); if (!fop->fn) { printf("VFP: could not find double op %d\n", FEXT_TO_IDX(inst)); @@ -1262,17 +1221,14 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr) type = (fop->flags & OP_SD) ? 's' : 'd'; if (op == FOP_EXT) - LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = op[%u] (d%u)", - vecitr >> FPSCR_LENGTH_BIT, - type, dest, dn, dm); + LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = op[%u] (d%u)", vecitr >> FPSCR_LENGTH_BIT, + type, dest, dn, dm); else LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)", - vecitr >> FPSCR_LENGTH_BIT, - type, dest, dn, FOP_TO_IDX(op), dm); + vecitr >> FPSCR_LENGTH_BIT, type, dest, dn, FOP_TO_IDX(op), dm); except = fop->fn(state, dest, dn, dm, fpscr); - LOG_TRACE(Core_ARM11, "VFP: itr%d: exceptions=%08x", - vecitr >> FPSCR_LENGTH_BIT, except); + LOG_TRACE(Core_ARM11, "VFP: itr%d: exceptions=%08x", vecitr >> FPSCR_LENGTH_BIT, except); exceptions |= except; diff --git a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp index 1a98d0114..a66dc1016 100644 --- a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp +++ b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp @@ -19,14 +19,13 @@ struct vmla_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vmla)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmla_inst)); - vmla_inst *inst_cream = (vmla_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vmla)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vmla_inst)); + vmla_inst* inst_cream = (vmla_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -35,12 +34,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmla)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VMLA_INST: -{ +VMLA_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vmla_inst *inst_cream = (vmla_inst *)inst_base->component; + vmla_inst* inst_cream = (vmla_inst*)inst_base->component; int ret; @@ -68,14 +66,13 @@ struct vmls_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vmls)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmls_inst)); - vmls_inst *inst_cream = (vmls_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vmls)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vmls_inst)); + vmls_inst* inst_cream = (vmls_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -84,12 +81,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmls)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VMLS_INST: -{ +VMLS_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vmls_inst *inst_cream = (vmls_inst *)inst_base->component; + vmls_inst* inst_cream = (vmls_inst*)inst_base->component; int ret; @@ -117,14 +113,13 @@ struct vnmla_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vnmla)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vnmla_inst)); - vnmla_inst *inst_cream = (vnmla_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vnmla)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vnmla_inst)); + vnmla_inst* inst_cream = (vnmla_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -133,12 +128,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vnmla)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VNMLA_INST: -{ +VNMLA_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vnmla_inst *inst_cream = (vnmla_inst *)inst_base->component; + vnmla_inst* inst_cream = (vnmla_inst*)inst_base->component; int ret; @@ -167,14 +161,13 @@ struct vnmls_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vnmls)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vnmls_inst)); - vnmls_inst *inst_cream = (vnmls_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vnmls)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vnmls_inst)); + vnmls_inst* inst_cream = (vnmls_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -183,12 +176,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vnmls)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VNMLS_INST: -{ +VNMLS_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vnmls_inst *inst_cream = (vnmls_inst *)inst_base->component; + vnmls_inst* inst_cream = (vnmls_inst*)inst_base->component; int ret; @@ -216,14 +208,13 @@ struct vnmul_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vnmul)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vnmul_inst)); - vnmul_inst *inst_cream = (vnmul_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vnmul)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vnmul_inst)); + vnmul_inst* inst_cream = (vnmul_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -232,12 +223,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vnmul)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VNMUL_INST: -{ +VNMUL_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vnmul_inst *inst_cream = (vnmul_inst *)inst_base->component; + vnmul_inst* inst_cream = (vnmul_inst*)inst_base->component; int ret; @@ -265,14 +255,13 @@ struct vmul_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vmul)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmul_inst)); - vmul_inst *inst_cream = (vmul_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vmul)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vmul_inst)); + vmul_inst* inst_cream = (vmul_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -281,12 +270,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmul)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VMUL_INST: -{ +VMUL_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vmul_inst *inst_cream = (vmul_inst *)inst_base->component; + vmul_inst* inst_cream = (vmul_inst*)inst_base->component; int ret; @@ -314,14 +302,13 @@ struct vadd_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vadd)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vadd_inst)); - vadd_inst *inst_cream = (vadd_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vadd)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vadd_inst)); + vadd_inst* inst_cream = (vadd_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -330,12 +317,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vadd)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VADD_INST: -{ +VADD_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vadd_inst *inst_cream = (vadd_inst *)inst_base->component; + vadd_inst* inst_cream = (vadd_inst*)inst_base->component; int ret; @@ -363,14 +349,13 @@ struct vsub_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vsub)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vsub_inst)); - vsub_inst *inst_cream = (vsub_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vsub)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vsub_inst)); + vsub_inst* inst_cream = (vsub_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -379,12 +364,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vsub)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VSUB_INST: -{ +VSUB_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vsub_inst *inst_cream = (vsub_inst *)inst_base->component; + vsub_inst* inst_cream = (vsub_inst*)inst_base->component; int ret; @@ -412,14 +396,13 @@ struct vdiv_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vdiv)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vdiv_inst)); - vdiv_inst *inst_cream = (vdiv_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vdiv)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vdiv_inst)); + vdiv_inst* inst_cream = (vdiv_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -428,12 +411,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vdiv)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VDIV_INST: -{ +VDIV_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vdiv_inst *inst_cream = (vdiv_inst *)inst_base->component; + vdiv_inst* inst_cream = (vdiv_inst*)inst_base->component; int ret; @@ -463,32 +445,33 @@ struct vmovi_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovi)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovi_inst)); - vmovi_inst *inst_cream = (vmovi_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovi)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vmovi_inst)); + vmovi_inst* inst_cream = (vmovi_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->single = BIT(inst, 8) == 0; - inst_cream->d = (inst_cream->single ? BITS(inst,12,15)<<1 | BIT(inst,22) : BITS(inst,12,15) | BIT(inst,22)<<4); + inst_cream->d = (inst_cream->single ? BITS(inst, 12, 15) << 1 | BIT(inst, 22) + : BITS(inst, 12, 15) | BIT(inst, 22) << 4); unsigned int imm8 = BITS(inst, 16, 19) << 4 | BITS(inst, 0, 3); if (inst_cream->single) - inst_cream->imm = BIT(imm8, 7)<<31 | (BIT(imm8, 6)==0)<<30 | (BIT(imm8, 6) ? 0x1f : 0)<<25 | BITS(imm8, 0, 5)<<19; + inst_cream->imm = BIT(imm8, 7) << 31 | (BIT(imm8, 6) == 0) << 30 | + (BIT(imm8, 6) ? 0x1f : 0) << 25 | BITS(imm8, 0, 5) << 19; else - inst_cream->imm = BIT(imm8, 7)<<31 | (BIT(imm8, 6)==0)<<30 | (BIT(imm8, 6) ? 0xff : 0)<<22 | BITS(imm8, 0, 5)<<16; + inst_cream->imm = BIT(imm8, 7) << 31 | (BIT(imm8, 6) == 0) << 30 | + (BIT(imm8, 6) ? 0xff : 0) << 22 | BITS(imm8, 0, 5) << 16; return inst_base; } #endif #ifdef VFP_INTERPRETER_IMPL -VMOVI_INST: -{ +VMOVI_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vmovi_inst *inst_cream = (vmovi_inst *)inst_base->component; + vmovi_inst* inst_cream = (vmovi_inst*)inst_base->component; VMOVI(cpu, inst_cream->single, inst_cream->d, inst_cream->imm); } @@ -511,28 +494,28 @@ struct vmovr_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovr)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovr_inst)); - vmovr_inst *inst_cream = (vmovr_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovr)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vmovr_inst)); + vmovr_inst* inst_cream = (vmovr_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->single = BIT(inst, 8) == 0; - inst_cream->d = (inst_cream->single ? BITS(inst,12,15)<<1 | BIT(inst,22) : BITS(inst,12,15) | BIT(inst,22)<<4); - inst_cream->m = (inst_cream->single ? BITS(inst, 0, 3)<<1 | BIT(inst, 5) : BITS(inst, 0, 3) | BIT(inst, 5)<<4); + inst_cream->d = (inst_cream->single ? BITS(inst, 12, 15) << 1 | BIT(inst, 22) + : BITS(inst, 12, 15) | BIT(inst, 22) << 4); + inst_cream->m = (inst_cream->single ? BITS(inst, 0, 3) << 1 | BIT(inst, 5) + : BITS(inst, 0, 3) | BIT(inst, 5) << 4); return inst_base; } #endif #ifdef VFP_INTERPRETER_IMPL -VMOVR_INST: -{ +VMOVR_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vmovr_inst *inst_cream = (vmovr_inst *)inst_base->component; + vmovr_inst* inst_cream = (vmovr_inst*)inst_base->component; VMOVR(cpu, inst_cream->single, inst_cream->d, inst_cream->m); } @@ -553,14 +536,13 @@ typedef struct _vabs_inst { } vabs_inst; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vabs)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vabs_inst)); - vabs_inst *inst_cream = (vabs_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vabs)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vabs_inst)); + vabs_inst* inst_cream = (vabs_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -569,12 +551,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vabs)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VABS_INST: -{ +VABS_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vabs_inst *inst_cream = (vabs_inst *)inst_base->component; + vabs_inst* inst_cream = (vabs_inst*)inst_base->component; int ret; @@ -603,14 +584,13 @@ struct vneg_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vneg)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vneg_inst)); - vneg_inst *inst_cream = (vneg_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vneg)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vneg_inst)); + vneg_inst* inst_cream = (vneg_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -619,12 +599,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vneg)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VNEG_INST: -{ +VNEG_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vneg_inst *inst_cream = (vneg_inst *)inst_base->component; + vneg_inst* inst_cream = (vneg_inst*)inst_base->component; int ret; @@ -652,14 +631,13 @@ struct vsqrt_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vsqrt)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vsqrt_inst)); - vsqrt_inst *inst_cream = (vsqrt_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vsqrt)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vsqrt_inst)); + vsqrt_inst* inst_cream = (vsqrt_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -668,12 +646,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vsqrt)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VSQRT_INST: -{ +VSQRT_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vsqrt_inst *inst_cream = (vsqrt_inst *)inst_base->component; + vsqrt_inst* inst_cream = (vsqrt_inst*)inst_base->component; int ret; @@ -701,14 +678,13 @@ struct vcmp_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcmp_inst)); - vcmp_inst *inst_cream = (vcmp_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vcmp_inst)); + vcmp_inst* inst_cream = (vcmp_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -717,12 +693,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VCMP_INST: -{ +VCMP_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vcmp_inst *inst_cream = (vcmp_inst *)inst_base->component; + vcmp_inst* inst_cream = (vcmp_inst*)inst_base->component; int ret; @@ -750,14 +725,13 @@ struct vcmp2_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp2)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcmp2_inst)); - vcmp2_inst *inst_cream = (vcmp2_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp2)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vcmp2_inst)); + vcmp2_inst* inst_cream = (vcmp2_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -766,12 +740,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp2)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VCMP2_INST: -{ +VCMP2_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vcmp2_inst *inst_cream = (vcmp2_inst *)inst_base->component; + vcmp2_inst* inst_cream = (vcmp2_inst*)inst_base->component; int ret; @@ -799,14 +772,13 @@ struct vcvtbds_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbds)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcvtbds_inst)); - vcvtbds_inst *inst_cream = (vcvtbds_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbds)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vcvtbds_inst)); + vcvtbds_inst* inst_cream = (vcvtbds_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -815,12 +787,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbds)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VCVTBDS_INST: -{ +VCVTBDS_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vcvtbds_inst *inst_cream = (vcvtbds_inst *)inst_base->component; + vcvtbds_inst* inst_cream = (vcvtbds_inst*)inst_base->component; int ret; @@ -848,16 +819,15 @@ struct vcvtbff_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbff)(unsigned int inst, int index) -{ +static ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbff)(unsigned int inst, int index) { VFP_DEBUG_UNTESTED(VCVTBFF); - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcvtbff_inst)); - vcvtbff_inst *inst_cream = (vcvtbff_inst *)inst_base->component; + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vcvtbff_inst)); + vcvtbff_inst* inst_cream = (vcvtbff_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -866,12 +836,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbff)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VCVTBFF_INST: -{ +VCVTBFF_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vcvtbff_inst *inst_cream = (vcvtbff_inst *)inst_base->component; + vcvtbff_inst* inst_cream = (vcvtbff_inst*)inst_base->component; int ret; @@ -899,14 +868,13 @@ struct vcvtbfi_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbfi)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcvtbfi_inst)); - vcvtbfi_inst *inst_cream = (vcvtbfi_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbfi)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vcvtbfi_inst)); + vcvtbfi_inst* inst_cream = (vcvtbfi_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->dp_operation = BIT(inst, 8); inst_cream->instr = inst; @@ -915,12 +883,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbfi)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VCVTBFI_INST: -{ +VCVTBFI_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vcvtbfi_inst *inst_cream = (vcvtbfi_inst *)inst_base->component; + vcvtbfi_inst* inst_cream = (vcvtbfi_inst*)inst_base->component; int ret; @@ -955,29 +922,27 @@ struct vmovbrs_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrs)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrs_inst)); - vmovbrs_inst *inst_cream = (vmovbrs_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrs)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrs_inst)); + vmovbrs_inst* inst_cream = (vmovbrs_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->to_arm = BIT(inst, 20) == 1; - inst_cream->t = BITS(inst, 12, 15); - inst_cream->n = BIT(inst, 7) | BITS(inst, 16, 19)<<1; + inst_cream->t = BITS(inst, 12, 15); + inst_cream->n = BIT(inst, 7) | BITS(inst, 16, 19) << 1; return inst_base; } #endif #ifdef VFP_INTERPRETER_IMPL -VMOVBRS_INST: -{ +VMOVBRS_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vmovbrs_inst *inst_cream = (vmovbrs_inst *)inst_base->component; + vmovbrs_inst* inst_cream = (vmovbrs_inst*)inst_base->component; VMOVBRS(cpu, inst_cream->to_arm, inst_cream->t, inst_cream->n, &(cpu->Reg[inst_cream->t])); } @@ -999,24 +964,22 @@ struct vmsr_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vmsr)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmsr_inst)); - vmsr_inst *inst_cream = (vmsr_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vmsr)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vmsr_inst)); + vmsr_inst* inst_cream = (vmsr_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->reg = BITS(inst, 16, 19); - inst_cream->Rt = BITS(inst, 12, 15); + inst_cream->Rt = BITS(inst, 12, 15); return inst_base; } #endif #ifdef VFP_INTERPRETER_IMPL -VMSR_INST: -{ +VMSR_INST : { if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { /* FIXME: special case for access to FPSID and FPEXC, VFP must be disabled , and in privileged mode */ @@ -1026,14 +989,11 @@ VMSR_INST: vmsr_inst* const inst_cream = (vmsr_inst*)inst_base->component; unsigned int reg = inst_cream->reg; - unsigned int rt = inst_cream->Rt; + unsigned int rt = inst_cream->Rt; - if (reg == 1) - { + if (reg == 1) { cpu->VFP[VFP_FPSCR] = cpu->Reg[rt]; - } - else if (cpu->InAPrivilegedMode()) - { + } else if (cpu->InAPrivilegedMode()) { if (reg == 8) cpu->VFP[VFP_FPEXC] = cpu->Reg[rt]; else if (reg == 9) @@ -1062,17 +1022,16 @@ struct vmovbrc_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrc)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrc_inst)); - vmovbrc_inst *inst_cream = (vmovbrc_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrc)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrc_inst)); + vmovbrc_inst* inst_cream = (vmovbrc_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->d = BITS(inst, 16, 19)|BIT(inst, 7)<<4; - inst_cream->t = BITS(inst, 12, 15); + inst_cream->d = BITS(inst, 16, 19) | BIT(inst, 7) << 4; + inst_cream->t = BITS(inst, 12, 15); /* VFP variant of instruction */ inst_cream->esize = 32; inst_cream->index = BIT(inst, 21); @@ -1081,8 +1040,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrc)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VMOVBRC_INST: -{ +VMOVBRC_INST : { if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; @@ -1108,24 +1066,22 @@ struct vmrs_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vmrs)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmrs_inst)); - vmrs_inst *inst_cream = (vmrs_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vmrs)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vmrs_inst)); + vmrs_inst* inst_cream = (vmrs_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->reg = BITS(inst, 16, 19); - inst_cream->Rt = BITS(inst, 12, 15); + inst_cream->Rt = BITS(inst, 12, 15); return inst_base; } #endif #ifdef VFP_INTERPRETER_IMPL -VMRS_INST: -{ +VMRS_INST : { if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { /* FIXME: special case for access to FPSID and FPEXC, VFP must be disabled, and in privileged mode */ @@ -1135,36 +1091,25 @@ VMRS_INST: vmrs_inst* const inst_cream = (vmrs_inst*)inst_base->component; unsigned int reg = inst_cream->reg; - unsigned int rt = inst_cream->Rt; + unsigned int rt = inst_cream->Rt; if (reg == 1) // FPSCR { - if (rt != 15) - { + if (rt != 15) { cpu->Reg[rt] = cpu->VFP[VFP_FPSCR]; - } - else - { + } else { cpu->NFlag = (cpu->VFP[VFP_FPSCR] >> 31) & 1; cpu->ZFlag = (cpu->VFP[VFP_FPSCR] >> 30) & 1; cpu->CFlag = (cpu->VFP[VFP_FPSCR] >> 29) & 1; cpu->VFlag = (cpu->VFP[VFP_FPSCR] >> 28) & 1; } - } - else if (reg == 0) - { + } else if (reg == 0) { cpu->Reg[rt] = cpu->VFP[VFP_FPSID]; - } - else if (reg == 6) - { + } else if (reg == 6) { cpu->Reg[rt] = cpu->VFP[VFP_MVFR1]; - } - else if (reg == 7) - { + } else if (reg == 7) { cpu->Reg[rt] = cpu->VFP[VFP_MVFR0]; - } - else if (cpu->InAPrivilegedMode()) - { + } else if (cpu->InAPrivilegedMode()) { if (reg == 8) cpu->Reg[rt] = cpu->VFP[VFP_FPEXC]; else if (reg == 9) @@ -1193,17 +1138,16 @@ struct vmovbcr_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbcr)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbcr_inst)); - vmovbcr_inst *inst_cream = (vmovbcr_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbcr)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbcr_inst)); + vmovbcr_inst* inst_cream = (vmovbcr_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->d = BITS(inst, 16, 19)|BIT(inst, 7)<<4; - inst_cream->t = BITS(inst, 12, 15); + inst_cream->d = BITS(inst, 16, 19) | BIT(inst, 7) << 4; + inst_cream->t = BITS(inst, 12, 15); /* VFP variant of instruction */ inst_cream->esize = 32; inst_cream->index = BIT(inst, 21); @@ -1212,12 +1156,11 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbcr)(unsigned int inst, int index) } #endif #ifdef VFP_INTERPRETER_IMPL -VMOVBCR_INST: -{ +VMOVBCR_INST : { if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vmovbcr_inst* const inst_cream = (vmovbcr_inst*) inst_base->component; + vmovbcr_inst* const inst_cream = (vmovbcr_inst*)inst_base->component; cpu->Reg[inst_cream->t] = cpu->ExtReg[(2 * inst_cream->d) + inst_cream->index]; } @@ -1246,33 +1189,31 @@ struct vmovbrrss_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrss)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrrss_inst)); - vmovbrrss_inst *inst_cream = (vmovbrrss_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrss)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrrss_inst)); + vmovbrrss_inst* inst_cream = (vmovbrrss_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->to_arm = BIT(inst, 20) == 1; - inst_cream->t = BITS(inst, 12, 15); - inst_cream->t2 = BITS(inst, 16, 19); - inst_cream->m = BITS(inst, 0, 3)<<1|BIT(inst, 5); + inst_cream->t = BITS(inst, 12, 15); + inst_cream->t2 = BITS(inst, 16, 19); + inst_cream->m = BITS(inst, 0, 3) << 1 | BIT(inst, 5); return inst_base; } #endif #ifdef VFP_INTERPRETER_IMPL -VMOVBRRSS_INST: -{ +VMOVBRRSS_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; vmovbrrss_inst* const inst_cream = (vmovbrrss_inst*)inst_base->component; VMOVBRRSS(cpu, inst_cream->to_arm, inst_cream->t, inst_cream->t2, inst_cream->m, - &cpu->Reg[inst_cream->t], &cpu->Reg[inst_cream->t2]); + &cpu->Reg[inst_cream->t], &cpu->Reg[inst_cream->t2]); } cpu->Reg[15] += cpu->GetInstructionSize(); INC_PC(sizeof(vmovbrrss_inst)); @@ -1294,33 +1235,31 @@ struct vmovbrrd_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrd)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrrd_inst)); - vmovbrrd_inst *inst_cream = (vmovbrrd_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrd)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrrd_inst)); + vmovbrrd_inst* inst_cream = (vmovbrrd_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->to_arm = BIT(inst, 20) == 1; - inst_cream->t = BITS(inst, 12, 15); - inst_cream->t2 = BITS(inst, 16, 19); - inst_cream->m = BIT(inst, 5)<<4 | BITS(inst, 0, 3); + inst_cream->t = BITS(inst, 12, 15); + inst_cream->t2 = BITS(inst, 16, 19); + inst_cream->m = BIT(inst, 5) << 4 | BITS(inst, 0, 3); return inst_base; } #endif #ifdef VFP_INTERPRETER_IMPL -VMOVBRRD_INST: -{ +VMOVBRRD_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vmovbrrd_inst *inst_cream = (vmovbrrd_inst *)inst_base->component; + vmovbrrd_inst* inst_cream = (vmovbrrd_inst*)inst_base->component; VMOVBRRD(cpu, inst_cream->to_arm, inst_cream->t, inst_cream->t2, inst_cream->m, - &(cpu->Reg[inst_cream->t]), &(cpu->Reg[inst_cream->t2])); + &(cpu->Reg[inst_cream->t]), &(cpu->Reg[inst_cream->t2])); } cpu->Reg[15] += cpu->GetInstructionSize(); INC_PC(sizeof(vmovbrrd_inst)); @@ -1347,43 +1286,40 @@ struct vstr_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vstr)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vstr_inst)); - vstr_inst *inst_cream = (vstr_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vstr)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vstr_inst)); + vstr_inst* inst_cream = (vstr_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->single = BIT(inst, 8) == 0; - inst_cream->add = BIT(inst, 23); - inst_cream->imm32 = BITS(inst, 0,7) << 2; - inst_cream->d = (inst_cream->single ? BITS(inst, 12, 15)<<1|BIT(inst, 22) : BITS(inst, 12, 15)|BIT(inst, 22)<<4); - inst_cream->n = BITS(inst, 16, 19); + inst_cream->add = BIT(inst, 23); + inst_cream->imm32 = BITS(inst, 0, 7) << 2; + inst_cream->d = (inst_cream->single ? BITS(inst, 12, 15) << 1 | BIT(inst, 22) + : BITS(inst, 12, 15) | BIT(inst, 22) << 4); + inst_cream->n = BITS(inst, 16, 19); return inst_base; } #endif #ifdef VFP_INTERPRETER_IMPL -VSTR_INST: -{ +VSTR_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vstr_inst *inst_cream = (vstr_inst *)inst_base->component; + vstr_inst* inst_cream = (vstr_inst*)inst_base->component; - unsigned int base = (inst_cream->n == 15 ? (cpu->Reg[inst_cream->n] & 0xFFFFFFFC) + 8 : cpu->Reg[inst_cream->n]); + unsigned int base = (inst_cream->n == 15 ? (cpu->Reg[inst_cream->n] & 0xFFFFFFFC) + 8 + : cpu->Reg[inst_cream->n]); addr = (inst_cream->add ? base + inst_cream->imm32 : base - inst_cream->imm32); - if (inst_cream->single) - { + if (inst_cream->single) { cpu->WriteMemory32(addr, cpu->ExtReg[inst_cream->d]); - } - else - { - const u32 word1 = cpu->ExtReg[inst_cream->d*2+0]; - const u32 word2 = cpu->ExtReg[inst_cream->d*2+1]; + } else { + const u32 word1 = cpu->ExtReg[inst_cream->d * 2 + 0]; + const u32 word2 = cpu->ExtReg[inst_cream->d * 2 + 1]; if (cpu->InBigEndianMode()) { cpu->WriteMemory32(addr + 0, word2); @@ -1413,44 +1349,39 @@ struct vpush_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vpush)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vpush_inst)); - vpush_inst *inst_cream = (vpush_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vpush)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vpush_inst)); + vpush_inst* inst_cream = (vpush_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->single = BIT(inst, 8) == 0; - inst_cream->d = (inst_cream->single ? BITS(inst, 12, 15)<<1|BIT(inst, 22) : BITS(inst, 12, 15)|BIT(inst, 22)<<4); - inst_cream->imm32 = BITS(inst, 0, 7)<<2; - inst_cream->regs = (inst_cream->single ? BITS(inst, 0, 7) : BITS(inst, 1, 7)); + inst_cream->single = BIT(inst, 8) == 0; + inst_cream->d = (inst_cream->single ? BITS(inst, 12, 15) << 1 | BIT(inst, 22) + : BITS(inst, 12, 15) | BIT(inst, 22) << 4); + inst_cream->imm32 = BITS(inst, 0, 7) << 2; + inst_cream->regs = (inst_cream->single ? BITS(inst, 0, 7) : BITS(inst, 1, 7)); return inst_base; } #endif #ifdef VFP_INTERPRETER_IMPL -VPUSH_INST: -{ +VPUSH_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vpush_inst *inst_cream = (vpush_inst *)inst_base->component; + vpush_inst* inst_cream = (vpush_inst*)inst_base->component; addr = cpu->Reg[R13] - inst_cream->imm32; - for (unsigned int i = 0; i < inst_cream->regs; i++) - { - if (inst_cream->single) - { - cpu->WriteMemory32(addr, cpu->ExtReg[inst_cream->d+i]); + for (unsigned int i = 0; i < inst_cream->regs; i++) { + if (inst_cream->single) { + cpu->WriteMemory32(addr, cpu->ExtReg[inst_cream->d + i]); addr += 4; - } - else - { - const u32 word1 = cpu->ExtReg[(inst_cream->d+i)*2+0]; - const u32 word2 = cpu->ExtReg[(inst_cream->d+i)*2+1]; + } else { + const u32 word1 = cpu->ExtReg[(inst_cream->d + i) * 2 + 0]; + const u32 word2 = cpu->ExtReg[(inst_cream->d + i) * 2 + 1]; if (cpu->InBigEndianMode()) { cpu->WriteMemory32(addr + 0, word2); @@ -1488,28 +1419,28 @@ struct vstm_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vstm)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vstm_inst)); - vstm_inst *inst_cream = (vstm_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vstm)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vstm_inst)); + vstm_inst* inst_cream = (vstm_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->single = BIT(inst, 8) == 0; - inst_cream->add = BIT(inst, 23); - inst_cream->wback = BIT(inst, 21); - inst_cream->d = (inst_cream->single ? BITS(inst, 12, 15)<<1|BIT(inst, 22) : BITS(inst, 12, 15)|BIT(inst, 22)<<4); - inst_cream->n = BITS(inst, 16, 19); - inst_cream->imm32 = BITS(inst, 0, 7)<<2; - inst_cream->regs = (inst_cream->single ? BITS(inst, 0, 7) : BITS(inst, 1, 7)); + inst_cream->add = BIT(inst, 23); + inst_cream->wback = BIT(inst, 21); + inst_cream->d = (inst_cream->single ? BITS(inst, 12, 15) << 1 | BIT(inst, 22) + : BITS(inst, 12, 15) | BIT(inst, 22) << 4); + inst_cream->n = BITS(inst, 16, 19); + inst_cream->imm32 = BITS(inst, 0, 7) << 2; + inst_cream->regs = (inst_cream->single ? BITS(inst, 0, 7) : BITS(inst, 1, 7)); return inst_base; } #endif #ifdef VFP_INTERPRETER_IMPL -VSTM_INST: /* encoding 1 */ +VSTM_INST : /* encoding 1 */ { if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; @@ -1525,17 +1456,13 @@ VSTM_INST: /* encoding 1 */ if (inst_cream->add == 0) address -= inst_cream->imm32; - for (unsigned int i = 0; i < inst_cream->regs; i++) - { - if (inst_cream->single) - { - cpu->WriteMemory32(address, cpu->ExtReg[inst_cream->d+i]); + for (unsigned int i = 0; i < inst_cream->regs; i++) { + if (inst_cream->single) { + cpu->WriteMemory32(address, cpu->ExtReg[inst_cream->d + i]); address += 4; - } - else - { - const u32 word1 = cpu->ExtReg[(inst_cream->d+i)*2+0]; - const u32 word2 = cpu->ExtReg[(inst_cream->d+i)*2+1]; + } else { + const u32 word1 = cpu->ExtReg[(inst_cream->d + i) * 2 + 0]; + const u32 word2 = cpu->ExtReg[(inst_cream->d + i) * 2 + 1]; if (cpu->InBigEndianMode()) { cpu->WriteMemory32(address + 0, word2); @@ -1549,8 +1476,9 @@ VSTM_INST: /* encoding 1 */ } } if (inst_cream->wback) { - cpu->Reg[inst_cream->n] = (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 : - cpu->Reg[inst_cream->n] - inst_cream->imm32); + cpu->Reg[inst_cream->n] = + (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 + : cpu->Reg[inst_cream->n] - inst_cream->imm32); } } cpu->Reg[15] += 4; @@ -1573,51 +1501,46 @@ struct vpop_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vpop)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vpop_inst)); - vpop_inst *inst_cream = (vpop_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vpop)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vpop_inst)); + vpop_inst* inst_cream = (vpop_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; - inst_cream->single = BIT(inst, 8) == 0; - inst_cream->d = (inst_cream->single ? (BITS(inst, 12, 15)<<1)|BIT(inst, 22) : BITS(inst, 12, 15)|(BIT(inst, 22)<<4)); - inst_cream->imm32 = BITS(inst, 0, 7)<<2; - inst_cream->regs = (inst_cream->single ? BITS(inst, 0, 7) : BITS(inst, 1, 7)); + inst_cream->single = BIT(inst, 8) == 0; + inst_cream->d = (inst_cream->single ? (BITS(inst, 12, 15) << 1) | BIT(inst, 22) + : BITS(inst, 12, 15) | (BIT(inst, 22) << 4)); + inst_cream->imm32 = BITS(inst, 0, 7) << 2; + inst_cream->regs = (inst_cream->single ? BITS(inst, 0, 7) : BITS(inst, 1, 7)); return inst_base; } #endif #ifdef VFP_INTERPRETER_IMPL -VPOP_INST: -{ +VPOP_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vpop_inst *inst_cream = (vpop_inst *)inst_base->component; + vpop_inst* inst_cream = (vpop_inst*)inst_base->component; addr = cpu->Reg[R13]; - for (unsigned int i = 0; i < inst_cream->regs; i++) - { - if (inst_cream->single) - { - cpu->ExtReg[inst_cream->d+i] = cpu->ReadMemory32(addr); + for (unsigned int i = 0; i < inst_cream->regs; i++) { + if (inst_cream->single) { + cpu->ExtReg[inst_cream->d + i] = cpu->ReadMemory32(addr); addr += 4; - } - else - { + } else { const u32 word1 = cpu->ReadMemory32(addr + 0); const u32 word2 = cpu->ReadMemory32(addr + 4); if (cpu->InBigEndianMode()) { - cpu->ExtReg[(inst_cream->d+i)*2+0] = word2; - cpu->ExtReg[(inst_cream->d+i)*2+1] = word1; + cpu->ExtReg[(inst_cream->d + i) * 2 + 0] = word2; + cpu->ExtReg[(inst_cream->d + i) * 2 + 1] = word1; } else { - cpu->ExtReg[(inst_cream->d+i)*2+0] = word1; - cpu->ExtReg[(inst_cream->d+i)*2+1] = word2; + cpu->ExtReg[(inst_cream->d + i) * 2 + 0] = word1; + cpu->ExtReg[(inst_cream->d + i) * 2 + 1] = word2; } addr += 8; @@ -1632,7 +1555,6 @@ VPOP_INST: } #endif - /* ----------------------------------------------------------------------- */ /* VLDR */ /* cond 1101 UD01 Rn-- Vd-- 101X imm8 imm8 */ @@ -1646,50 +1568,47 @@ struct vldr_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vldr)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vldr_inst)); - vldr_inst *inst_cream = (vldr_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vldr)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vldr_inst)); + vldr_inst* inst_cream = (vldr_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->single = BIT(inst, 8) == 0; - inst_cream->add = BIT(inst, 23); - inst_cream->imm32 = BITS(inst, 0,7) << 2; - inst_cream->d = (inst_cream->single ? BITS(inst, 12, 15)<<1|BIT(inst, 22) : BITS(inst, 12, 15)|BIT(inst, 22)<<4); - inst_cream->n = BITS(inst, 16, 19); + inst_cream->add = BIT(inst, 23); + inst_cream->imm32 = BITS(inst, 0, 7) << 2; + inst_cream->d = (inst_cream->single ? BITS(inst, 12, 15) << 1 | BIT(inst, 22) + : BITS(inst, 12, 15) | BIT(inst, 22) << 4); + inst_cream->n = BITS(inst, 16, 19); return inst_base; } #endif #ifdef VFP_INTERPRETER_IMPL -VLDR_INST: -{ +VLDR_INST : { if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; - vldr_inst *inst_cream = (vldr_inst *)inst_base->component; + vldr_inst* inst_cream = (vldr_inst*)inst_base->component; - unsigned int base = (inst_cream->n == 15 ? (cpu->Reg[inst_cream->n] & 0xFFFFFFFC) + 8 : cpu->Reg[inst_cream->n]); + unsigned int base = (inst_cream->n == 15 ? (cpu->Reg[inst_cream->n] & 0xFFFFFFFC) + 8 + : cpu->Reg[inst_cream->n]); addr = (inst_cream->add ? base + inst_cream->imm32 : base - inst_cream->imm32); - if (inst_cream->single) - { + if (inst_cream->single) { cpu->ExtReg[inst_cream->d] = cpu->ReadMemory32(addr); - } - else - { + } else { const u32 word1 = cpu->ReadMemory32(addr + 0); const u32 word2 = cpu->ReadMemory32(addr + 4); if (cpu->InBigEndianMode()) { - cpu->ExtReg[inst_cream->d*2+0] = word2; - cpu->ExtReg[inst_cream->d*2+1] = word1; + cpu->ExtReg[inst_cream->d * 2 + 0] = word2; + cpu->ExtReg[inst_cream->d * 2 + 1] = word1; } else { - cpu->ExtReg[inst_cream->d*2+0] = word1; - cpu->ExtReg[inst_cream->d*2+1] = word2; + cpu->ExtReg[inst_cream->d * 2 + 0] = word1; + cpu->ExtReg[inst_cream->d * 2 + 1] = word2; } } } @@ -1715,29 +1634,28 @@ struct vldm_inst { }; #endif #ifdef VFP_INTERPRETER_TRANS -static ARM_INST_PTR INTERPRETER_TRANSLATE(vldm)(unsigned int inst, int index) -{ - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vldm_inst)); - vldm_inst *inst_cream = (vldm_inst *)inst_base->component; +static ARM_INST_PTR INTERPRETER_TRANSLATE(vldm)(unsigned int inst, int index) { + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(vldm_inst)); + vldm_inst* inst_cream = (vldm_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = TransExtData::NON_BRANCH; + inst_base->idx = index; + inst_base->br = TransExtData::NON_BRANCH; inst_cream->single = BIT(inst, 8) == 0; - inst_cream->add = BIT(inst, 23); - inst_cream->wback = BIT(inst, 21); - inst_cream->d = (inst_cream->single ? BITS(inst, 12, 15)<<1|BIT(inst, 22) : BITS(inst, 12, 15)|BIT(inst, 22)<<4); - inst_cream->n = BITS(inst, 16, 19); - inst_cream->imm32 = BITS(inst, 0, 7)<<2; - inst_cream->regs = (inst_cream->single ? BITS(inst, 0, 7) : BITS(inst, 1, 7)); + inst_cream->add = BIT(inst, 23); + inst_cream->wback = BIT(inst, 21); + inst_cream->d = (inst_cream->single ? BITS(inst, 12, 15) << 1 | BIT(inst, 22) + : BITS(inst, 12, 15) | BIT(inst, 22) << 4); + inst_cream->n = BITS(inst, 16, 19); + inst_cream->imm32 = BITS(inst, 0, 7) << 2; + inst_cream->regs = (inst_cream->single ? BITS(inst, 0, 7) : BITS(inst, 1, 7)); return inst_base; } #endif #ifdef VFP_INTERPRETER_IMPL -VLDM_INST: -{ +VLDM_INST : { if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { CHECK_VFP_ENABLED; @@ -1752,32 +1670,29 @@ VLDM_INST: if (inst_cream->add == 0) address -= inst_cream->imm32; - for (unsigned int i = 0; i < inst_cream->regs; i++) - { - if (inst_cream->single) - { - cpu->ExtReg[inst_cream->d+i] = cpu->ReadMemory32(address); + for (unsigned int i = 0; i < inst_cream->regs; i++) { + if (inst_cream->single) { + cpu->ExtReg[inst_cream->d + i] = cpu->ReadMemory32(address); address += 4; - } - else - { + } else { const u32 word1 = cpu->ReadMemory32(address + 0); const u32 word2 = cpu->ReadMemory32(address + 4); if (cpu->InBigEndianMode()) { - cpu->ExtReg[(inst_cream->d+i)*2+0] = word2; - cpu->ExtReg[(inst_cream->d+i)*2+1] = word1; + cpu->ExtReg[(inst_cream->d + i) * 2 + 0] = word2; + cpu->ExtReg[(inst_cream->d + i) * 2 + 1] = word1; } else { - cpu->ExtReg[(inst_cream->d+i)*2+0] = word1; - cpu->ExtReg[(inst_cream->d+i)*2+1] = word2; + cpu->ExtReg[(inst_cream->d + i) * 2 + 0] = word1; + cpu->ExtReg[(inst_cream->d + i) * 2 + 1] = word2; } address += 8; } } if (inst_cream->wback) { - cpu->Reg[inst_cream->n] = (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 : - cpu->Reg[inst_cream->n] - inst_cream->imm32); + cpu->Reg[inst_cream->n] = + (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 + : cpu->Reg[inst_cream->n] - inst_cream->imm32); } } cpu->Reg[15] += cpu->GetInstructionSize(); diff --git a/src/core/arm/skyeye_common/vfp/vfpsingle.cpp b/src/core/arm/skyeye_common/vfp/vfpsingle.cpp index 60264f9b3..3c21efe62 100644 --- a/src/core/arm/skyeye_common/vfp/vfpsingle.cpp +++ b/src/core/arm/skyeye_common/vfp/vfpsingle.cpp @@ -58,24 +58,20 @@ #include "common/common_types.h" #include "common/logging/log.h" -#include "core/arm/skyeye_common/vfp/vfp_helper.h" #include "core/arm/skyeye_common/vfp/asm_vfp.h" #include "core/arm/skyeye_common/vfp/vfp.h" +#include "core/arm/skyeye_common/vfp/vfp_helper.h" static struct vfp_single vfp_single_default_qnan = { - 255, - 0, - VFP_SINGLE_SIGNIFICAND_QNAN, + 255, 0, VFP_SINGLE_SIGNIFICAND_QNAN, }; -static void vfp_single_dump(const char *str, struct vfp_single *s) -{ - LOG_TRACE(Core_ARM11, "%s: sign=%d exponent=%d significand=%08x", - str, s->sign != 0, s->exponent, s->significand); +static void vfp_single_dump(const char* str, struct vfp_single* s) { + LOG_TRACE(Core_ARM11, "%s: sign=%d exponent=%d significand=%08x", str, s->sign != 0, + s->exponent, s->significand); } -static void vfp_single_normalise_denormal(struct vfp_single *vs) -{ +static void vfp_single_normalise_denormal(struct vfp_single* vs) { int bits = 31 - fls(vs->significand); vfp_single_dump("normalise_denormal: in", vs); @@ -88,9 +84,8 @@ static void vfp_single_normalise_denormal(struct vfp_single *vs) vfp_single_dump("normalise_denormal: out", vs); } - -u32 vfp_single_normaliseround(ARMul_State* state, int sd, struct vfp_single *vs, u32 fpscr, const char *func) -{ +u32 vfp_single_normaliseround(ARMul_State* state, int sd, struct vfp_single* vs, u32 fpscr, + const char* func) { u32 significand, incr, rmode; int exponent, shift, underflow; u32 exceptions = 0; @@ -199,7 +194,7 @@ u32 vfp_single_normaliseround(ARMul_State* state, int sd, struct vfp_single *vs, vs->exponent = 253; vs->significand = 0x7fffffff; } else { - vs->exponent = 255; /* infinity */ + vs->exponent = 255; /* infinity */ vs->significand = 0; } } else { @@ -217,8 +212,7 @@ pack: vfp_single_dump("pack: final", vs); { s32 d = vfp_single_pack(vs); - LOG_TRACE(Core_ARM11, "%s: d(s%d)=%08x exceptions=%08x", func, - sd, d, exceptions); + LOG_TRACE(Core_ARM11, "%s: d(s%d)=%08x exceptions=%08x", func, sd, d, exceptions); vfp_put_float(state, d, sd); } @@ -229,11 +223,9 @@ pack: * Propagate the NaN, setting exceptions if it is signalling. * 'n' is always a NaN. 'm' may be a number, NaN or infinity. */ -static u32 -vfp_propagate_nan(struct vfp_single *vsd, struct vfp_single *vsn, - struct vfp_single *vsm, u32 fpscr) -{ - struct vfp_single *nan; +static u32 vfp_propagate_nan(struct vfp_single* vsd, struct vfp_single* vsn, struct vfp_single* vsm, + u32 fpscr) { + struct vfp_single* nan; int tn, tm = 0; tn = vfp_single_type(vsn); @@ -270,40 +262,33 @@ vfp_propagate_nan(struct vfp_single *vsd, struct vfp_single *vsn, return tn == VFP_SNAN || tm == VFP_SNAN ? FPSCR_IOC : VFP_NAN_FLAG; } - /* * Extended operations */ -static u32 vfp_single_fabs(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) -{ +static u32 vfp_single_fabs(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) { vfp_put_float(state, vfp_single_packed_abs(m), sd); return 0; } -static u32 vfp_single_fcpy(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) -{ +static u32 vfp_single_fcpy(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) { vfp_put_float(state, m, sd); return 0; } -static u32 vfp_single_fneg(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) -{ +static u32 vfp_single_fneg(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) { vfp_put_float(state, vfp_single_packed_negate(m), sd); return 0; } -static const u16 sqrt_oddadjust[] = { - 0x0004, 0x0022, 0x005d, 0x00b1, 0x011d, 0x019f, 0x0236, 0x02e0, - 0x039c, 0x0468, 0x0545, 0x0631, 0x072b, 0x0832, 0x0946, 0x0a67 -}; +static const u16 sqrt_oddadjust[] = {0x0004, 0x0022, 0x005d, 0x00b1, 0x011d, 0x019f, + 0x0236, 0x02e0, 0x039c, 0x0468, 0x0545, 0x0631, + 0x072b, 0x0832, 0x0946, 0x0a67}; -static const u16 sqrt_evenadjust[] = { - 0x0a2d, 0x08af, 0x075a, 0x0629, 0x051a, 0x0429, 0x0356, 0x029e, - 0x0200, 0x0179, 0x0109, 0x00af, 0x0068, 0x0034, 0x0012, 0x0002 -}; +static const u16 sqrt_evenadjust[] = {0x0a2d, 0x08af, 0x075a, 0x0629, 0x051a, 0x0429, + 0x0356, 0x029e, 0x0200, 0x0179, 0x0109, 0x00af, + 0x0068, 0x0034, 0x0012, 0x0002}; -u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand) -{ +u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand) { int index; u32 z, a; @@ -331,25 +316,24 @@ u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand) } } -static u32 vfp_single_fsqrt(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) -{ +static u32 vfp_single_fsqrt(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) { struct vfp_single vsm, vsd, *vsp; int ret, tm; u32 exceptions = 0; exceptions |= vfp_single_unpack(&vsm, m, fpscr); tm = vfp_single_type(&vsm); - if (tm & (VFP_NAN|VFP_INFINITY)) { + if (tm & (VFP_NAN | VFP_INFINITY)) { vsp = &vsd; if (tm & VFP_NAN) ret = vfp_propagate_nan(vsp, &vsm, nullptr, fpscr); else if (vsm.sign == 0) { -sqrt_copy: + sqrt_copy: vsp = &vsm; ret = 0; } else { -sqrt_invalid: + sqrt_invalid: vsp = &vfp_single_default_qnan; ret = FPSCR_IOC; } @@ -420,15 +404,15 @@ sqrt_invalid: * Greater than := C * Unordered := CV */ -static u32 vfp_compare(ARMul_State* state, int sd, int signal_on_qnan, s32 m, u32 fpscr) -{ +static u32 vfp_compare(ARMul_State* state, int sd, int signal_on_qnan, s32 m, u32 fpscr) { s32 d; u32 ret = 0; d = vfp_get_float(state, sd); if (vfp_single_packed_exponent(m) == 255 && vfp_single_packed_mantissa(m)) { ret |= FPSCR_CFLAG | FPSCR_VFLAG; - if (signal_on_qnan || !(vfp_single_packed_mantissa(m) & (1 << (VFP_SINGLE_MANTISSA_BITS - 1)))) + if (signal_on_qnan || + !(vfp_single_packed_mantissa(m) & (1 << (VFP_SINGLE_MANTISSA_BITS - 1)))) /* * Signalling NaN, or signalling on quiet NaN */ @@ -437,7 +421,8 @@ static u32 vfp_compare(ARMul_State* state, int sd, int signal_on_qnan, s32 m, u3 if (vfp_single_packed_exponent(d) == 255 && vfp_single_packed_mantissa(d)) { ret |= FPSCR_CFLAG | FPSCR_VFLAG; - if (signal_on_qnan || !(vfp_single_packed_mantissa(d) & (1 << (VFP_SINGLE_MANTISSA_BITS - 1)))) + if (signal_on_qnan || + !(vfp_single_packed_mantissa(d) & (1 << (VFP_SINGLE_MANTISSA_BITS - 1)))) /* * Signalling NaN, or signalling on quiet NaN */ @@ -479,28 +464,23 @@ static u32 vfp_compare(ARMul_State* state, int sd, int signal_on_qnan, s32 m, u3 return ret; } -static u32 vfp_single_fcmp(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) -{ +static u32 vfp_single_fcmp(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) { return vfp_compare(state, sd, 0, m, fpscr); } -static u32 vfp_single_fcmpe(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) -{ +static u32 vfp_single_fcmpe(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) { return vfp_compare(state, sd, 1, m, fpscr); } -static u32 vfp_single_fcmpz(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) -{ +static u32 vfp_single_fcmpz(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) { return vfp_compare(state, sd, 0, 0, fpscr); } -static u32 vfp_single_fcmpez(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) -{ +static u32 vfp_single_fcmpez(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) { return vfp_compare(state, sd, 1, 0, fpscr); } -static u32 vfp_single_fcvtd(ARMul_State* state, int dd, int unused, s32 m, u32 fpscr) -{ +static u32 vfp_single_fcvtd(ARMul_State* state, int dd, int unused, s32 m, u32 fpscr) { struct vfp_single vsm; struct vfp_double vdd; int tm; @@ -525,7 +505,7 @@ static u32 vfp_single_fcvtd(ARMul_State* state, int dd, int unused, s32 m, u32 f /* * If we have an infinity or NaN, the exponent must be 2047. */ - if (tm & (VFP_INFINITY|VFP_NAN)) { + if (tm & (VFP_INFINITY | VFP_NAN)) { vdd.exponent = 2047; if (tm == VFP_QNAN) vdd.significand |= VFP_DOUBLE_SIGNIFICAND_QNAN; @@ -543,8 +523,7 @@ pack_nan: return exceptions; } -static u32 vfp_single_fuito(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) -{ +static u32 vfp_single_fuito(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) { struct vfp_single vs; u32 exceptions = 0; @@ -556,8 +535,7 @@ static u32 vfp_single_fuito(ARMul_State* state, int sd, int unused, s32 m, u32 f return exceptions; } -static u32 vfp_single_fsito(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) -{ +static u32 vfp_single_fsito(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) { struct vfp_single vs; u32 exceptions = 0; @@ -569,8 +547,7 @@ static u32 vfp_single_fsito(ARMul_State* state, int sd, int unused, s32 m, u32 f return exceptions; } -static u32 vfp_single_ftoui(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) -{ +static u32 vfp_single_ftoui(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) { struct vfp_single vsm; u32 d, exceptions = 0; int rmode = fpscr & FPSCR_RMODE_MASK; @@ -656,13 +633,11 @@ static u32 vfp_single_ftoui(ARMul_State* state, int sd, int unused, s32 m, u32 f return exceptions; } -static u32 vfp_single_ftouiz(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) -{ +static u32 vfp_single_ftouiz(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) { return vfp_single_ftoui(state, sd, unused, m, (fpscr & ~FPSCR_RMODE_MASK) | FPSCR_ROUND_TOZERO); } -static u32 vfp_single_ftosi(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) -{ +static u32 vfp_single_ftosi(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) { struct vfp_single vsm; u32 d, exceptions = 0; int rmode = fpscr & FPSCR_RMODE_MASK; @@ -739,51 +714,44 @@ static u32 vfp_single_ftosi(ARMul_State* state, int sd, int unused, s32 m, u32 f return exceptions; } -static u32 vfp_single_ftosiz(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) -{ +static u32 vfp_single_ftosiz(ARMul_State* state, int sd, int unused, s32 m, u32 fpscr) { return vfp_single_ftosi(state, sd, unused, m, (fpscr & ~FPSCR_RMODE_MASK) | FPSCR_ROUND_TOZERO); } static struct op fops_ext[] = { - { vfp_single_fcpy, 0 }, //0x00000000 - FEXT_FCPY - { vfp_single_fabs, 0 }, //0x00000001 - FEXT_FABS - { vfp_single_fneg, 0 }, //0x00000002 - FEXT_FNEG - { vfp_single_fsqrt, 0 }, //0x00000003 - FEXT_FSQRT - { nullptr, 0 }, - { nullptr, 0 }, - { nullptr, 0 }, - { nullptr, 0 }, - { vfp_single_fcmp, OP_SCALAR }, //0x00000008 - FEXT_FCMP - { vfp_single_fcmpe, OP_SCALAR }, //0x00000009 - FEXT_FCMPE - { vfp_single_fcmpz, OP_SCALAR }, //0x0000000A - FEXT_FCMPZ - { vfp_single_fcmpez, OP_SCALAR }, //0x0000000B - FEXT_FCMPEZ - { nullptr, 0 }, - { nullptr, 0 }, - { nullptr, 0 }, - { vfp_single_fcvtd, OP_SCALAR|OP_DD }, //0x0000000F - FEXT_FCVT - { vfp_single_fuito, OP_SCALAR }, //0x00000010 - FEXT_FUITO - { vfp_single_fsito, OP_SCALAR }, //0x00000011 - FEXT_FSITO - { nullptr, 0 }, - { nullptr, 0 }, - { nullptr, 0 }, - { nullptr, 0 }, - { nullptr, 0 }, - { nullptr, 0 }, - { vfp_single_ftoui, OP_SCALAR }, //0x00000018 - FEXT_FTOUI - { vfp_single_ftouiz, OP_SCALAR }, //0x00000019 - FEXT_FTOUIZ - { vfp_single_ftosi, OP_SCALAR }, //0x0000001A - FEXT_FTOSI - { vfp_single_ftosiz, OP_SCALAR }, //0x0000001B - FEXT_FTOSIZ + {vfp_single_fcpy, 0}, // 0x00000000 - FEXT_FCPY + {vfp_single_fabs, 0}, // 0x00000001 - FEXT_FABS + {vfp_single_fneg, 0}, // 0x00000002 - FEXT_FNEG + {vfp_single_fsqrt, 0}, // 0x00000003 - FEXT_FSQRT + {nullptr, 0}, + {nullptr, 0}, + {nullptr, 0}, + {nullptr, 0}, + {vfp_single_fcmp, OP_SCALAR}, // 0x00000008 - FEXT_FCMP + {vfp_single_fcmpe, OP_SCALAR}, // 0x00000009 - FEXT_FCMPE + {vfp_single_fcmpz, OP_SCALAR}, // 0x0000000A - FEXT_FCMPZ + {vfp_single_fcmpez, OP_SCALAR}, // 0x0000000B - FEXT_FCMPEZ + {nullptr, 0}, + {nullptr, 0}, + {nullptr, 0}, + {vfp_single_fcvtd, OP_SCALAR | OP_DD}, // 0x0000000F - FEXT_FCVT + {vfp_single_fuito, OP_SCALAR}, // 0x00000010 - FEXT_FUITO + {vfp_single_fsito, OP_SCALAR}, // 0x00000011 - FEXT_FSITO + {nullptr, 0}, + {nullptr, 0}, + {nullptr, 0}, + {nullptr, 0}, + {nullptr, 0}, + {nullptr, 0}, + {vfp_single_ftoui, OP_SCALAR}, // 0x00000018 - FEXT_FTOUI + {vfp_single_ftouiz, OP_SCALAR}, // 0x00000019 - FEXT_FTOUIZ + {vfp_single_ftosi, OP_SCALAR}, // 0x0000001A - FEXT_FTOSI + {vfp_single_ftosiz, OP_SCALAR}, // 0x0000001B - FEXT_FTOSIZ }; - - - - -static u32 -vfp_single_fadd_nonnumber(struct vfp_single *vsd, struct vfp_single *vsn, - struct vfp_single *vsm, u32 fpscr) -{ - struct vfp_single *vsp; +static u32 vfp_single_fadd_nonnumber(struct vfp_single* vsd, struct vfp_single* vsn, + struct vfp_single* vsm, u32 fpscr) { + struct vfp_single* vsp; u32 exceptions = 0; int tn, tm; @@ -821,14 +789,11 @@ vfp_single_fadd_nonnumber(struct vfp_single *vsd, struct vfp_single *vsn, return exceptions; } -static u32 -vfp_single_add(struct vfp_single *vsd, struct vfp_single *vsn, - struct vfp_single *vsm, u32 fpscr) -{ +static u32 vfp_single_add(struct vfp_single* vsd, struct vfp_single* vsn, struct vfp_single* vsm, + u32 fpscr) { u32 exp_diff, m_sig; - if (vsn->significand & 0x80000000 || - vsm->significand & 0x80000000) { + if (vsn->significand & 0x80000000 || vsm->significand & 0x80000000) { LOG_WARNING(Core_ARM11, "bad FP values"); vfp_single_dump("VSN", vsn); vfp_single_dump("VSM", vsm); @@ -872,8 +837,7 @@ vfp_single_add(struct vfp_single *vsd, struct vfp_single *vsn, vsd->sign = vfp_sign_negate(vsd->sign); m_sig = (~m_sig + 1); } else if (m_sig == 0) { - vsd->sign = (fpscr & FPSCR_RMODE_MASK) == - FPSCR_ROUND_MINUSINF ? 0x8000 : 0; + vsd->sign = (fpscr & FPSCR_RMODE_MASK) == FPSCR_ROUND_MINUSINF ? 0x8000 : 0; } } else { m_sig = vsn->significand + m_sig; @@ -883,9 +847,8 @@ vfp_single_add(struct vfp_single *vsd, struct vfp_single *vsn, return 0; } -static u32 -vfp_single_multiply(struct vfp_single *vsd, struct vfp_single *vsn, struct vfp_single *vsm, u32 fpscr) -{ +static u32 vfp_single_multiply(struct vfp_single* vsd, struct vfp_single* vsn, + struct vfp_single* vsm, u32 fpscr) { vfp_single_dump("VSN", vsn); vfp_single_dump("VSM", vsm); @@ -938,12 +901,11 @@ vfp_single_multiply(struct vfp_single *vsd, struct vfp_single *vsn, struct vfp_s return 0; } -#define NEG_MULTIPLY (1 << 0) -#define NEG_SUBTRACT (1 << 1) +#define NEG_MULTIPLY (1 << 0) +#define NEG_SUBTRACT (1 << 1) -static u32 -vfp_single_multiply_accumulate(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr, u32 negate, const char *func) -{ +static u32 vfp_single_multiply_accumulate(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr, + u32 negate, const char* func) { vfp_single vsd, vsp, vsn, vsm; u32 exceptions = 0; s32 v; @@ -985,8 +947,7 @@ vfp_single_multiply_accumulate(ARMul_State* state, int sd, int sn, s32 m, u32 fp /* * sd = sd + (sn * sm) */ -static u32 vfp_single_fmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) -{ +static u32 vfp_single_fmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) { u32 exceptions = 0; LOG_TRACE(Core_ARM11, "s%u = %08x", sn, sd); exceptions |= vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, 0, "fmac"); @@ -996,8 +957,7 @@ static u32 vfp_single_fmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) /* * sd = sd - (sn * sm) */ -static u32 vfp_single_fnmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) -{ +static u32 vfp_single_fnmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) { // TODO: this one has its arguments inverted, investigate. LOG_TRACE(Core_ARM11, "s%u = %08x", sd, sn); return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, NEG_MULTIPLY, "fnmac"); @@ -1006,8 +966,7 @@ static u32 vfp_single_fnmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr /* * sd = -sd + (sn * sm) */ -static u32 vfp_single_fmsc(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) -{ +static u32 vfp_single_fmsc(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) { LOG_TRACE(Core_ARM11, "s%u = %08x", sn, sd); return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, NEG_SUBTRACT, "fmsc"); } @@ -1015,17 +974,16 @@ static u32 vfp_single_fmsc(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) /* * sd = -sd - (sn * sm) */ -static u32 vfp_single_fnmsc(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) -{ +static u32 vfp_single_fnmsc(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) { LOG_TRACE(Core_ARM11, "s%u = %08x", sn, sd); - return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, NEG_SUBTRACT | NEG_MULTIPLY, "fnmsc"); + return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, NEG_SUBTRACT | NEG_MULTIPLY, + "fnmsc"); } /* * sd = sn * sm */ -static u32 vfp_single_fmul(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) -{ +static u32 vfp_single_fmul(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) { struct vfp_single vsd, vsn, vsm; u32 exceptions = 0; s32 n = vfp_get_float(state, sn); @@ -1049,8 +1007,7 @@ static u32 vfp_single_fmul(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) /* * sd = -(sn * sm) */ -static u32 vfp_single_fnmul(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) -{ +static u32 vfp_single_fnmul(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) { struct vfp_single vsd, vsn, vsm; u32 exceptions = 0; s32 n = vfp_get_float(state, sn); @@ -1075,8 +1032,7 @@ static u32 vfp_single_fnmul(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr /* * sd = sn + sm */ -static u32 vfp_single_fadd(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) -{ +static u32 vfp_single_fadd(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) { struct vfp_single vsd, vsn, vsm; u32 exceptions = 0; s32 n = vfp_get_float(state, sn); @@ -1103,8 +1059,7 @@ static u32 vfp_single_fadd(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) /* * sd = sn - sm */ -static u32 vfp_single_fsub(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) -{ +static u32 vfp_single_fsub(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) { LOG_TRACE(Core_ARM11, "s%u = %08x", sn, sd); /* * Subtraction is addition with one sign inverted. @@ -1118,8 +1073,7 @@ static u32 vfp_single_fsub(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) /* * sd = sn / sm */ -static u32 vfp_single_fdiv(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) -{ +static u32 vfp_single_fdiv(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) { struct vfp_single vsd, vsn, vsm; u32 exceptions = 0; s32 n = vfp_get_float(state, sn); @@ -1151,7 +1105,7 @@ static u32 vfp_single_fdiv(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) * If n and m are infinity, the result is invalid * If n and m are zero, the result is invalid */ - if (tm & tn & (VFP_INFINITY|VFP_ZERO)) + if (tm & tn & (VFP_INFINITY | VFP_ZERO)) goto invalid; /* @@ -1226,29 +1180,22 @@ invalid: } static struct op fops[] = { - { vfp_single_fmac, 0 }, - { vfp_single_fmsc, 0 }, - { vfp_single_fmul, 0 }, - { vfp_single_fadd, 0 }, - { vfp_single_fnmac, 0 }, - { vfp_single_fnmsc, 0 }, - { vfp_single_fnmul, 0 }, - { vfp_single_fsub, 0 }, - { vfp_single_fdiv, 0 }, + {vfp_single_fmac, 0}, {vfp_single_fmsc, 0}, {vfp_single_fmul, 0}, + {vfp_single_fadd, 0}, {vfp_single_fnmac, 0}, {vfp_single_fnmsc, 0}, + {vfp_single_fnmul, 0}, {vfp_single_fsub, 0}, {vfp_single_fdiv, 0}, }; -#define FREG_BANK(x) ((x) & 0x18) -#define FREG_IDX(x) ((x) & 7) +#define FREG_BANK(x) ((x)&0x18) +#define FREG_IDX(x) ((x)&7) -u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr) -{ +u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr) { u32 op = inst & FOP_MASK; u32 exceptions = 0; unsigned int dest; unsigned int sn = vfp_get_sn(inst); unsigned int sm = vfp_get_sm(inst); unsigned int vecitr, veclen, vecstride; - struct op *fop; + struct op* fop; vecstride = 1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK); @@ -1274,11 +1221,11 @@ u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr) else veclen = fpscr & FPSCR_LENGTH_MASK; - LOG_TRACE(Core_ARM11, "vecstride=%u veclen=%u", vecstride, - (veclen >> FPSCR_LENGTH_BIT) + 1); + LOG_TRACE(Core_ARM11, "vecstride=%u veclen=%u", vecstride, (veclen >> FPSCR_LENGTH_BIT) + 1); if (!fop->fn) { - LOG_CRITICAL(Core_ARM11, "could not find single op %d, inst=0x%x@0x%x", FEXT_TO_IDX(inst), inst, state->Reg[15]); + LOG_CRITICAL(Core_ARM11, "could not find single op %d, inst=0x%x@0x%x", FEXT_TO_IDX(inst), + inst, state->Reg[15]); Crash(); goto invalid; } @@ -1290,17 +1237,14 @@ u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr) type = (fop->flags & OP_DD) ? 'd' : 's'; if (op == FOP_EXT) - LOG_TRACE(Core_ARM11, "itr%d (%c%u) = op[%u] (s%u=%08x)", - vecitr >> FPSCR_LENGTH_BIT, type, dest, sn, - sm, m); + LOG_TRACE(Core_ARM11, "itr%d (%c%u) = op[%u] (s%u=%08x)", vecitr >> FPSCR_LENGTH_BIT, + type, dest, sn, sm, m); else LOG_TRACE(Core_ARM11, "itr%d (%c%u) = (s%u) op[%u] (s%u=%08x)", - vecitr >> FPSCR_LENGTH_BIT, type, dest, sn, - FOP_TO_IDX(op), sm, m); + vecitr >> FPSCR_LENGTH_BIT, type, dest, sn, FOP_TO_IDX(op), sm, m); except = fop->fn(state, dest, sn, m, fpscr); - LOG_TRACE(Core_ARM11, "itr%d: exceptions=%08x", - vecitr >> FPSCR_LENGTH_BIT, except); + LOG_TRACE(Core_ARM11, "itr%d: exceptions=%08x", vecitr >> FPSCR_LENGTH_BIT, except); exceptions |= except; |