diff options
author | Lioncash <mathew1800@gmail.com> | 2014-12-30 15:42:29 +0100 |
---|---|---|
committer | Lioncash <mathew1800@gmail.com> | 2014-12-30 17:04:22 +0100 |
commit | 6ce4b7b6665e92a60fcd03ae0a008b455f812b12 (patch) | |
tree | 2070f7d5801855fde50a45089d53d13091eb7a77 /src/core/arm/skyeye_common/vfp/vfp.cpp | |
parent | Merge pull request #370 from lioncash/moresat (diff) | |
download | yuzu-6ce4b7b6665e92a60fcd03ae0a008b455f812b12.tar yuzu-6ce4b7b6665e92a60fcd03ae0a008b455f812b12.tar.gz yuzu-6ce4b7b6665e92a60fcd03ae0a008b455f812b12.tar.bz2 yuzu-6ce4b7b6665e92a60fcd03ae0a008b455f812b12.tar.lz yuzu-6ce4b7b6665e92a60fcd03ae0a008b455f812b12.tar.xz yuzu-6ce4b7b6665e92a60fcd03ae0a008b455f812b12.tar.zst yuzu-6ce4b7b6665e92a60fcd03ae0a008b455f812b12.zip |
Diffstat (limited to '')
-rw-r--r-- | src/core/arm/skyeye_common/vfp/vfp.cpp | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/src/core/arm/skyeye_common/vfp/vfp.cpp b/src/core/arm/skyeye_common/vfp/vfp.cpp index 5c036caeb..10d640f37 100644 --- a/src/core/arm/skyeye_common/vfp/vfp.cpp +++ b/src/core/arm/skyeye_common/vfp/vfp.cpp @@ -141,7 +141,7 @@ unsigned VFPMRRC(ARMul_State* state, unsigned type, u32 instr, u32* value1, u32* { if (CoProc == 10 && (OPC_1 & 0xD) == 1) { - VFP_DEBUG_UNIMPLEMENTED(VMOVBRRSS); + VMOVBRRSS(state, BIT(20), Rt, Rt2, BIT(5)<<4|CRm, value1, value2); return ARMul_DONE; } @@ -175,7 +175,7 @@ unsigned VFPMCRR(ARMul_State* state, unsigned type, u32 instr, u32 value1, u32 v { if (CoProc == 10 && (OPC_1 & 0xD) == 1) { - VFP_DEBUG_UNIMPLEMENTED(VMOVBRRSS); + VMOVBRRSS(state, BIT(20), Rt, Rt2, BIT(5)<<4|CRm, &value1, &value2); return ARMul_DONE; } @@ -504,6 +504,22 @@ void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword state->ExtReg[n*2] = *value1; } } +void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2) +{ + DBG("VMOV(BRRSS) :\n"); + if (to_arm) + { + DBG("\tr[%d-%d] <= s[%d-%d]=[%x-%x]\n", t2, t, n+1, n, state->ExtReg[n+1], state->ExtReg[n]); + *value1 = state->ExtReg[n+0]; + *value2 = state->ExtReg[n+1]; + } + else + { + DBG("\ts[%d-%d] <= r[%d-%d]=[%x-%x]\n", n+1, n, t2, t, *value2, *value1); + state->ExtReg[n+0] = *value1; + state->ExtReg[n+1] = *value2; + } +} /* ----------- MCR ------------ */ void VMSR(ARMul_State* state, ARMword reg, ARMword Rt) |