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authorarchshift <gh@archshift.com>2016-06-11 03:45:48 +0200
committerarchshift <gh@archshift.com>2016-06-11 03:45:48 +0200
commit765eef33197c55b524b9880c24fc9dcb8cf451fb (patch)
tree78bfb06ef6f62db334914d5a140448764d489ddb /src/core/arm/dyncom/arm_dyncom_interpreter.cpp
parentarm_dyncom_interpreter: rename operation functions to fit style guide (diff)
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Diffstat (limited to '')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index acf66b350..7f6cf6e29 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -753,6 +753,21 @@ static get_addr_fp_t GetAddressingOp(unsigned int inst) {
return nullptr;
}
+// Specialized for LDRT, LDRBT, STRT, and STRBT, which have specific addressing mode requirements
+get_addr_fp_t GetAddressingOpLoadStoreT(unsigned int inst) {
+ if (BITS(inst, 25, 27) == 2) {
+ return LnSWoUB(ImmediatePostIndexed);
+ } else if (BITS(inst, 25, 27) == 3) {
+ return LnSWoUB(ScaledRegisterPostIndexed);
+ }
+ // Reaching this would indicate the thumb version
+ // of this instruction, however the 3DS CPU doesn't
+ // support this variant (the 3DS CPU is only ARMv6K,
+ // while this variant is added in ARMv6T2).
+ // So it's sufficient for citra to not implement this.
+ return nullptr;
+}
+
typedef ARM_INST_PTR (*transop_fp_t)(unsigned int, int);
#include "arm_dyncom_trans.inc"